Parallelized scrubbing transactions

1. An apparatus, comprising:

a central processing unit (CPU) core; and

a cache subsystem coupled to the CPU core, the cache subsystem comprising:

a first memory;

a second memory;

a controller coupled to the first and second memories, the controller configured to:

execute a sequence of scrubbing transactions on the first memory; and

execute a functional transaction that is not a scrubbing transaction on thi second memory;

wherein a first scrubbing transaction of the sequence of scrubbing transactions and the functional transaction are executed concurrently;

a first pipeline coupled to the first memory and to the controller, the first pipeline comprising a first scrubber state machine;

a second pipeline coupled to the second memory and to the controller, the second pipeline comprising a second scrubber state machine; and

a scrubber control register comprising an enable field, a burst delay field, and a cycle delay field;

wherein the first pipeline is configured to process the first scrubbing transaction while the second pipeline processes the functional transaction.

2. The apparatus of claim 1 , wherein:

the sequence of scrubbing transactions comprises a first sequence;

the functional transaction comprises a first functional transaction; and

at a time after the first sequence of scrubbing transactions is executed on the first memory, the controller is further configured to:

execute a second sequence of scrubbing transactions on the second memory; and

execute a second functional transaction that is not a scrubbing transaction on the first memory;

wherein one of the second sequence of scrubbing transactions and the second functional transaction are executed concurrently.

3. The apparatus of claim 1 , wherein the first scrubber state machine is configured to:

in response to the enable field being asserted, begin a countdown timer comprising a countdown value based on a value of the cycle delay field;

in response to the countdown timer, transmit a scrub burst request and assert a stall request signal to the controller; and

receive a flush acknowledge signal from the controller and, in response to the flush acknowledge signal being asserted, begin the sequence of scrubbing transactions; wherein the controller is further configured to:

in response to the stall request signal being asserted, prevent new transactions from entering the first pipeline; and

in response to the first pipeline being flushed of in-flight transactions, assert the flush acknowledge signal.

4. The apparatus of claim 3 , wherein when the controller is configured to perform the first scrubbing transaction, the controller is further configured to:

re-calculate an error correcting code (ECC) syndrome for a line of data at an address in the first memory specified by the scrub burst request;

determine that a single error is present in the line of data based on a comparison of the re-calculated ECC syndrome and a stored ECC syndrome for the line of data;

overwrite the line of data in the first memory with a corrected line of data, wherein the single error is corrected in the corrected line of data; and

update the stored ECC syndrome based on the corrected line of data.

5. The apparatus of claim 3 , wherein when the controller is configured to perform the first scrubbing transaction, the controller is further configured to:

re-calculate an error correcting code (ECC) syndrome for a line of data at an address in the first memory specified by the scrub burst request;

determine that more than one error is present in the line of data based on a comparison of the re-calculated ECC syndrome and a stored ECC syndrome for the line of data; and

generate an interrupt in response to the determination that more than one error is present in the line of data.

6. The apparatus of claim 3 , wherein the controller is configured to perform a scrub burst as a series of scrubbing transactions on a predetermined number of consecutive addresses in the first memory.

7. The apparatus of claim 3 , wherein the countdown value comprises an integer multiple of the cycle delay field.

8. The apparatus of claim 1 , wherein the cache subsystem further comprises:

a test control register comprising a test enable field, a test address field, and a test count field.

9. The apparatus of claim 8 , wherein the first scrubber state machine is configured to:

in response to the enable field and the test enable field being asserted, begin a countdown timer comprising a countdown value based on a value of the cycle delay field;

in response to the countdown timer, assert a stall request signal to the controller; and

receive a flush acknowledge signal from the controller and, in response to the flush acknowledge signal being asserted, transmit a scrub burst request to the controller;

wherein the controller is further configured to:

in response to the stall request signal being asserted, prevent new transactions from entering the first pipeline;

in response to the first pipeline being flushed of in-flight transactions, assert the flush acknowledge signal; and

in response to receiving the scrub burst request, perform the sequence of scrubbing transactions beginning at an address specified by the test address field and continuing for a number of scrubbing transactions specified by the test count field.

10. A method, comprising:

providing a scrubber control register comprising an enable field, a burst delay field, and a cycle delay field;

executing, using a controller, a sequence of error correcting code (ECC) scrubbing transactions on a first memory, by:

in response to the enable field being asserted, beginning a countdown timer comprising a countdown value based on a value of the cycle delay field;

in response to the countdown timer, asserting a stall request signal to the controller;

in response to the stall request signal being asserted, preventing, by the controller, new transactions from entering a first pipeline coupled to the first memory;

in response to the first pipeline being flushed of in-flight transactions, asserting, by the controller, a flush acknowledge signal;

in response to the flush acknowledge signal being asserted, transmitting a scrub burst request to the controller; and

in response to receiving the scrub burst request, performing, by the controller, a scrubbing transaction of the sequence of ECC scrubbing transactions by processing, by a first pipeline coupled to the first memory, the scrubbing transaction; and

executing, by the controller, a functional transaction that is not an ECC scrubbing transaction on a second memory; and

at the same time as the processing the sequence of scrubbing transactions, processing, by a second pipeline coupled to the second memory, the functional transaction.

11. The method of claim 10 , wherein:

the sequence of scrubbing transactions comprises a first sequence;

the functional transaction comprises a first functional transaction; and

at a time after executing the first sequence of scrubbing transactions on the first memory, the method further comprises:

executing, by the controller, a second sequence of scrubbing transactions on the second memory; and

executing, by the controller, a second functional transaction that is not an ECC scrubbing transaction on the first memory;

wherein one of the second sequence of scrubbing transactions and the second functional transaction are executed concurrently.

12. The method of claim 10 , wherein performing the scrubbing transaction further comprises:

re-calculating an ECC syndrome for a line of data at an address in the first memory specified by the scrub burst request;

determining that a single error is present in the line of data based on a comparison of the re-calculated ECC syndrome and a stored ECC syndrome for the line of data;

overwriting the line of data in the first memory with a corrected line of data, wherein the single error is corrected in the corrected line of data; and

updating the stored ECC syndrome based on the corrected line of data.

13. The method of claim 10 , wherein performing the scrubbing transaction further comprises:

re-calculating an error correcting code (ECC) syndrome for a line of data at an address in the first memory specified by the scrub burst request;

determining that more than one error is present in the line of data based on a comparison of the re-calculated ECC syndrome and a stored ECC syndrome for the line of data; and

generating an interrupt in response to the determination that more than one error is present in the line of data.

14. The method of claim 10 , further comprising performing, by the controller, a scrub burst as a series of scrubbing transactions on a predetermined number of consecutive addresses in the first memory.

15. The method of claim 10 , wherein the countdown value comprises an integer multiple of the cycle delay field.

16. A device comprising:

a cache memory that includes a set of memory blocks;

a set of cache pipelines coupled to the set of memory blocks such that each cache pipeline of the set of cache pipelines is coupled to a respective memory block of the set of memory blocks, wherein each cache pipeline of the set of cache pipelines is configured to perform an error correcting code (ECC) scrubbing transaction on the respective memory block concurrent with another cache pipeline of the set of cache pipelines performing a transaction that is not an ECC scrubbing transaction;

a memory controller coupled to the set of cache pipelines and configured to perform a set of ECC scrubbing transactions on the set of memory blocks, wherein the set of ECC scrubbing transactions are grouped into bursts of consecutive scrubbing transactions and cycles of bursts; and

a control register configured to store a scrubber enable value, a first delay value that specifies a delay between consecutive bursts of the bursts, and a second delay value that specifies a delay between consecutive cycles of the cycles of bursts.

17. The device of claim 16 further comprising a test register configured to store at least one of: a starting address value or a count of scrub accesses in a scrub burst.