Semiconductor memory device

1. A semiconductor memory device, comprising:

a memory cell array having a plurality of memory strings spaced from each other in a first direction, each memory string having a first selection transistor, a first memory cell, a second memory cell, a third memory cell, and a second selection transistor connected in series;

a plurality of word lines spaced from each other in a second direction which intersects the first direction;

a first word line in the plurality of word lines is connected to gates of all first memory cells in the memory cell array;

a second word line in the plurality of word lines is connected to gates of all second memory cells in the memory cell array;

a third word line in the plurality of word lines is connected to gates of all third memory cells in the memory cell array;

a plurality of bit lines that are each connected to first selection transistors of the memory strings;

a plurality of first selection gate lines that are each connected to gates of the first selection transistors;

a plurality of second selection gate lines that are each connected to gates of the second selection transistors;

a source line that is connected to each of the second selection transistors; and

a controller configured to, during a read operation:

apply a first voltage to the first selection gate lines during a first period of the read operation, the first voltage being sufficient to turn on the first selection transistors, and

apply a second voltage to each of the first selection gate lines connected to non-selected memory strings during a second period of the read operation after the first period, the second voltage being higher than a ground voltage and lower than the first voltage, wherein

when the controller reads data from the second memory cells included in a target row of the memory strings, the read operation further includes:

applying a third voltage to the first word line and the third word line and a fourth voltage to the second word line during the second period, the third voltage being higher than the second voltage, the fourth voltage being lower than the third voltage.

2. The semiconductor memory device according to claim 1 , wherein each memory cell is configured to store data of more than two bits.

3. The semiconductor memory device according to claim 1 , wherein the plurality of second selection gate lines are connected to each other.

4. The semiconductor memory device according to claim 1 , wherein the read operation further includes:

continuously applying a fifth voltage to the source line from the first period to a third period that is during the read operation but after the second period.

5. The semiconductor memory device according to claim 4 , wherein the read operation further includes:

applying the fifth voltage to the bit lines in the first period, and

applying a sixth voltage to the bit lines in the second period, the sixth voltage being higher than the fifth voltage.

6. The semiconductor memory device according to claim 4 , wherein the read operation further includes:

applying the fifth voltage to the bit lines in the first period,

applying the a sixth voltage to the bit lines in the second period, and

applying the sixth voltage to the bit lines in the third period, the sixth voltage being higher than the fifth voltage.

7. The semiconductor memory device according to claim 1 , wherein the plurality of cells are NAND type flash memory cells.

8. The semiconductor memory device according to claim 1 , wherein the read operation further includes:

continuously applying the second voltage to each of the first selection gate lines connected to non-selected memory strings during a third period after the second period.

9. The semiconductor memory device according to claim 8 , wherein the third period is before a reset period that is after an end of the read operation.

10. A semiconductor memory device, comprising:

a controller configured to cause data stored in a first memory cell of a first memory string in a memory cell array to be read by performing a read operation, the read operation including:

in a first period, applying a first voltage to a first selection gate line connected to a gate of a first selection transistor of the first memory string and to a second selection gate line connected to a gate of a second selection transistor of the first memory string,

in a second period after the first period, applying a second voltage to the first selection gate line and the second selection gate line to turn on the first selection transistor and a third selection transistor of a second memory string, the second voltage being higher than the first voltage, the second memory string without a memory cell being read in the read operation, and

in a third period after the second period, applying a third voltage to a fourth selection transistor of the second memory string, the third voltage being greater than the first voltage and less than the second voltage.

11. The semiconductor memory device according to claim 10 , further comprising:

a word line connected to gates of the first memory cell and a second memory cell, the second memory cell being in the second memory string; and

a bit line connected to the first selection transistor and the third selection transistor.

12. The semiconductor memory device according to claim 11 , wherein each of the first and second memory cell are each configured to store more than two bits of data.

13. The semiconductor memory device according to claim 10 , wherein each of the first and second memory cells are configured to store more than two bits of data.

14. The semiconductor memory device according to claim 13 , wherein the first and second memory cells are NAND type flash memory.

15. The semiconductor memory device according to claim 10 , wherein the first and second memory cells are NAND type flash memory.

16. The semiconductor memory device according to claim 10 , wherein the read operation further includes:

maintaining the second voltage on the first selection transistor, the second selection transistor, and the third selection transistor in the third period.