Memory systems and methods of correcting errors in the memory systems

1. A memory system comprising:

a memory medium;

a loop-buffer configured to store read data outputted from the memory medium in a first operation mode;

a fake-command generator configured to generate a fake-command in a second operation mode; and

an error correction code (ECC) decoder configured to perform an ECC decoding operation of the read data stored in the loop-buffer in response to the fake-command.

2. The memory system of claim 1 ,

wherein the memory medium includes a plurality of memory chips; and

wherein the read data includes a plurality of data stored in respective ones of the plurality of memory chips.

3. The memory system of claim 1 , further comprising an uncorrectable-error (UE) handler configured to receive ECC decoded read data from the ECC decoder to determine one of the first operation mode and the second operation mode to perform as an operation mode.

4. The memory system of claim 3 , wherein the UE handler determines the first operation mode to perform as an operation mode when errors of the read data outputted from the memory medium have not been corrected by the ECC decoder.

5. The memory system of claim 3 , wherein the UE handler determines the second operation mode to perform as an operation mode after the first operation mode when errors of the read data outputted from the memory medium have not been corrected by the ECC decoder.

6. The memory system of claim 1 , wherein the ECC decoder receives the read data outputted from the memory medium to perform the ECC decoding operation on the read data using a general Reed-Solomon (RS) algorithm system, in the first operation mode.

7. The memory system of claim 1 , wherein the ECC decoder performs the ECC decoding operation on the read data received from the loop-buffer using an erasure-loop method in the second operation mode.

8. The memory system of claim 1 , wherein an operation for accessing to the memory medium is at least one of interrupted and prevented when the fake-command is generated.

9. A memory system comprising:

a memory medium;

a command control unit configured to generate a preliminary fake-command control signal and a fake-command in a first operation mode and a second operation mode, respectively;

a loop-buffer configured to store read data outputted from the memory medium in response to the preliminary fake-command control signal in the first operation mode and configured to output read data stored in the loop-buffer in response to the fake-command in the second operation mode;

a loop-counter configured to perform a reset operation in response to the preliminary fake-command control signal in the first operation mode and configured to output a count value of the loop-counter in response to the fake-command in the second operation mode; and

an error correction code (ECC) decoder configured to perform a first ECC decoding operation of the read data outputted from the memory medium in the first operation mode and configured to perform a second ECC decoding operation of the read data outputted from the loop-buffer in the second operation mode.

10. The memory system of claim 9 ,

wherein the memory medium includes a plurality of memory chips; and

wherein the read data includes a plurality of data stored in respective ones of the plurality of memory chips.

11. The memory system of claim 9 , wherein the command control unit includes:

an uncorrectable-error (UE) handler configured to generate the preliminary fake-command control signal in the first operation mode and configured to generate a fake-command control signal in the second operation mode; and

a fake-command generator configured to generate the fake-command in response to the fake-command control signal in the second operation mode.

12. The memory system of claim 11 ,

wherein the UE handler generates the preliminary fake-command control signal when errors of the read data outputted from the memory medium are not corrected by a previous ECC decoding operation; and

wherein the UE handler generates the fake-command control signal when errors of the read data outputted from the memory medium are not corrected by an ECC decoding operation in the first operation mode.

13. The memory system of claim 9 , further comprising a memory interface logic circuit configured to access to the memory medium in response to the preliminary fake-command control signal and configured to interrupt the access to the memory medium in response to the fake-command.

14. The memory system of claim 13 ,

wherein the memory interface logic circuit is configured to output first to third control signals to each of the loop-buffer, the loop-counter and the ECC decoder in the first operation mode and the second operation mode;

wherein the first control signal indicates one of activation and inactivation of the second operation mode;

wherein the second control signal has a value of an index; and

wherein the third control signal indicates one of activation and inactivation of the first operation mode.

15. The memory system of claim 14 ,

wherein the loop-buffer includes a plurality of buffer regions which are distinguished from each other by the index of the second control signal;

wherein the loop-buffer stores the read data into a buffer region designated by the index of the second control signal among the plurality of buffer regions in response to the third control signal indicating the first operation mode; and

wherein the loop-buffer outputs the read data stored in the buffer region designated by the index of the second control signal among the plurality of buffer regions in response to the first control signal indicating the second operation mode.

16. The memory system of claim 15 ,

wherein the loop-counter includes a plurality of counters which are distinguished from each other by the index of the second control signal;

wherein the loop-counter resets a counter designated by the index of the second control signal among the plurality of counters in response to the third control signal indicating the first operation mode; and

wherein the loop-counter performs a counting operation for outputting and increasing a count value of a counter designated by the index of the second control signal among the plurality of counters in response to the first control signal indicating the second operation mode.

17. The memory system of claim 9 ,

wherein the ECC decoder performs the first ECC decoding operation using a general Reed-Solomon (RS) algorithm system in the first operation mode; and

wherein the ECC decoder performs the second ECC decoding operation using an erasure-loop method erasing symbols designated by a count value outputted from the loop-counter in the second operation mode.

18. The memory system of claim 9 , further comprising a multiplexer configured to receiving read data from the memory medium through a first input terminal, configured to receive read data stored in the loop-buffer through a second input terminal, and configured to selectively output the read data inputted through the first input terminal or the read data inputted through the second input terminal to the ECC decoder according to whether the fake-command is inputted to a control terminal of the multiplexer.