Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
1. A semiconductor device, comprising:
a first metal interconnection and a second metal interconnection on a substrate;
a first inter-metal dielectric (IMD) layer around the first metal interconnection and the second metal interconnection;
a channel layer on the first IMD layer, the first metal interconnection, and the second metal interconnection, wherein a sidewall of the channel layer comprises a curve; and
a magnetic tunneling junction (MTJ) on the channel layer.
2. The semiconductor device of claim 1 , wherein the channel layer comprises:
a first channel layer on the first metal interconnection and the second metal interconnection; and
a second channel layer on the first channel layer.
3. The semiconductor device of claim 2 , wherein a sidewall of the first channel layer comprises a first curve.
4. The semiconductor device of claim 2 , wherein a sidewall of the second channel layer comprises a second curve.
5. The semiconductor device of claim 2 , further comprising a dielectric layer around the first channel layer.
6. The semiconductor device of claim 5 , wherein a top surface of the dielectric layer comprises a third curve.
7. The semiconductor device of claim 2 , wherein the first channel layer and the second channel layer comprise different materials.
8. The semiconductor device of claim 1 , wherein a sidewall of the MTJ comprises a fourth curve.
9. The semiconductor device of claim 1 , wherein the MTJ comprises:
a free layer on the channel layer;
a barrier layer on the free layer; and
a pinned layer on the barrier layer.
10. The semiconductor device of claim 1 , further comprising:
a cap layer on the channel layer and adjacent to the MTJ; and
a second IMD layer around the cap layer.