Semiconductor structure and manufacturing method of the same
The present disclosure provides a semiconductor structure, including a memory region, a first metal line in the memory region, a magnetic tunneling junction (MTJ) cell over the first metal line, a carbon-based layer between the first metal line and the MTJ cell, a second metal line over the MTJ cell, a logic region adjacent to the memory region, wherein the logic region is free from a coverage of the carbon-based layer.
1. A semiconductor structure, comprising:
a memory region;
a first metal line in the memory region;
a magnetic tunneling junction (MTJ) cell over the first metal line;
a carbon-based layer between the first metal line and the MTJ cell, wherein the carbon-based layer comprises a first portion proximal to the MTJ cell and a second portion adjacent to the first portion, a thickness of the first portion is greater than a thickness of the second portion;
a second metal line over the MTJ cell;
a logic region adjacent to the memory region, wherein the logic region is free from a coverage of the carbon-based layer.
2. The semiconductor structure of claim 1 , further comprising a bottom electrode via under the MTJ cell and over the first metal line, wherein the bottom electrode via is laterally surrounded by the carbon-based layer.
3. The semiconductor structure of claim 1 , further comprising a planarization etch stop layer over the carbon-based layer.
4. The semiconductor structure of claim 3 , wherein the planarization etch stop layer is only under a coverage of a vertical projection area of the MTJ cell.
5. The semiconductor structure of claim 3 , wherein the planarization etch stop layer comprises silicon-rich oxide.
6. The semiconductor structure of claim 1 , wherein the carbon-based layer is composed of carbon, amorphous carbon, or diamond.
7. The semiconductor structure of claim 2 , wherein the bottom electrode via has a profile tapering away from the MTJ cell, the MTJ cell is a profile tapering away from the bottom electrode via.
8. A semiconductor structure, comprising:
a logic region;
a memory region adjacent to the logic region;
a first metal line in the memory region;
a bottom electrode via over the first metal line;
an interlayer dielectric partially surrounding the bottom electrode via;
a magnetic tunneling junction (MTJ) cell over the bottom electrode via;
a carbon-based layer between the first metal line and the MTJ cell, wherein at least a portion of the interlayer dielectric is exposed from the carbon-based layer;
a second metal line over the MTJ cell; and
a sidewall spacer laterally surrounding a sidewall of the MTJ cell and an upper portion of the bottom electrode via, wherein the sidewall spacer is in direct contact with the carbon-based layer.
9. The semiconductor structure of claim 8 , wherein an interface between the MTJ cell and the bottom electrode via is above a top surface of the carbon-based layer.
10. The semiconductor structure of claim 8 , wherein a top width of the bottom electrode via is identical with a bottom width of the MTJ cell.
11. The semiconductor structure of claim 8 , wherein the carbon-based layer is composed of carbon, amorphous carbon, or diamond.
12. The semiconductor structure of claim 8 , wherein the bottom electrode via has a profile tapering away from the MTJ cell, the MTJ cell is a profile tapering away from the bottom electrode via.
13. A semiconductor structure, comprising:
a logic region;
a memory region adjacent to the logic region;
a first metal line in the memory region;
a bottom electrode via over the first metal line;
a magnetic tunneling junction (MTJ) cell over the bottom electrode via;
a first etch stop layer between the first metal line and the MTJ cell, wherein a thickness of a first portion of the first etch stop layer directly under the MTJ cell is greater than a thickness of a second portion of the first etch stop layer free from a coverage of a vertical projection area of the MTJ cell;
a second metal line over the MTJ cell.
14. The semiconductor structure of claim 13 , further comprising a second etch stop layer laterally surrounding a top portion of the bottom electrode via and in direct contact with the first etch stop layer.
15. The semiconductor structure of claim 14 , wherein the second etch stop layer is between the first portion of the first etch stop layer and a bottom surface of the MTJ cell.
16. The semiconductor structure of claim 14 , wherein the second etch stop layer is only under a vertical projection area of the MTJ cell.
17. The semiconductor structure of claim 13 , further comprising a sidewall spacer laterally surrounding a top portion of the bottom electrode via and a sidewall of the MTJ cell.
18. The semiconductor structure of claim 14 , further comprising a sidewall spacer in direct contact with a sidewall of the second etch stop layer.
19. The semiconductor structure of claim 13 , wherein the logic region is free from a coverage of the first etch stop layer.
20. The semiconductor structure of claim 14 , wherein the first etch stop layer comprises carbon-based material, and the second etch stop layer comprises silicon-rich oxide.