Disk drive biasing two write assist elements using three terminal control circuitry
A data storage device is disclosed comprising a storage medium and a head configured to access the storage medium, wherein the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal. The second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node. A first bias signal is applied to the first terminal of the WA1, a second bias signal is applied to the first terminal of the WA2, and a common mode voltage is applied to the common node.
1. Control circuitry comprising:
a first current source configured to apply a first bias current to a first terminal of a first write assist element (WA1) of a data storage device;
a second current source configured to apply a second bias current to a first terminal of a second write assist element (WA2) of the data storage device; and
a voltage generator configured to apply a common mode voltage to a common node of the WA1 and WA2, wherein the voltage generator comprises an amplifier configured to generate the common mode voltage.
2. The control circuitry as recited in claim 1 , wherein:
an output of the amplifier is coupled to the first current source through a first isolation capacitor configured to isolate a first termination resistor from the first bias current; and
the output of the amplifier is coupled to the second current source through a second isolation capacitor configured to isolate a second termination resistor from the second bias current.
3. The control circuitry as recited in claim 1 , further comprising:
a first terminal of a first termination resistor coupled through a first isolation capacitor to the first current source to isolate the first termination resistor from the first bias current; and
a first terminal of a second termination resistor coupled through a second isolation capacitor to the second current source to isolate the second termination resistor from the second bias current;
wherein a second terminal of the first termination resistor and a second terminal of the second termination resistor are coupled together.
4. The control circuitry as recited in claim 1 , wherein the common mode voltage is different than a voltage potential of a storage medium of the data storage device.
5. The control circuitry as recited in claim 1 , further comprising:
a first output configured to couple to a first transmission line coupled to the first terminal of the WA1;
a second output configured to couple to a second transmission line coupled to the first terminal of the WA2; and
a third output configured to couple to a third transmission line coupled to the common node.
6. The control circuitry as recited in claim 5 , wherein the control circuitry comprises a third current source configured to apply a third bias current to the third transmission line, wherein the third bias current substantially equals a sum of the first bias current and the second bias current.
7. A data storage device comprising:
a storage medium;
a head configured to access the storage medium, wherein:
the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal; and
the second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node; and
control circuitry configured to:
apply a first bias signal to the first terminal of the WA1;
apply a second bias signal to the first terminal of the WA2; and
apply a common mode voltage to the common node, wherein the control circuitry comprises an amplifier configured to generate the common mode voltage.
8. The data storage device as recited in claim 7 , wherein the common mode voltage is different than a voltage potential of the storage medium.
9. The data storage device as recited in claim 7 , wherein the first bias signal comprises a first bias current and the second bias signal comprises a second bias current.
10. The data storage device as recited in claim 9 , wherein the control circuitry further comprises:
a first terminal of a first termination resistor coupled through a first isolation capacitor to the first terminal of the WA1 to isolate the first termination resistor from the first bias current; and
a first terminal of a second termination resistor coupled through a second isolation capacitor to the first terminal of the WA2 to isolate the second termination resistor from the second bias current;
wherein a second terminal of the first termination resistor and a second terminal of the second termination resistor are coupled together.
11. The data storage device as recited in claim 9 , wherein:
an output of the amplifier is coupled to the first terminal of the WA1 through a first isolation capacitor configured to isolate a first termination resistor from the first bias current; and
the output of the amplifier is coupled to the first terminal of the WA2 through a second isolation capacitor configured to isolate a second termination resistor from the second bias current.
12. The data storage device as recited in claim 9 , further comprising:
a first transmission line coupling the control circuitry to the first terminal of the WA1;
a second transmission line coupling the control circuitry to the first terminal of the WA2; and
a third transmission line coupling the control circuitry to the common node.
13. The data storage device as recited in claim 12 , wherein the control circuitry comprises:
a first current source configured to apply the first bias current to the first transmission line;
a second current source configured to apply the second bias current to the second transmission line; and
a third current source configured to apply a third bias current to the third transmission line, wherein the third bias current substantially equals a sum of the first bias current and the second bias current.
14. A data storage device comprising:
a storage medium;
a head configured to access the storage medium, wherein:
the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal; and
the second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node; and
a means for biasing the first terminal of the WA1;
a means for biasing the first terminal of the WA2; and
a means for voltage biasing the common node of the WA1and the WA2, wherein the means for voltage biasing the common node comprises an amplifier configured to generate a common mode voltage.
15. A data storage device comprising:
a storage medium;
a head configured to access the storage medium, wherein:
the head comprises a first write assist element (WA1) comprising a first terminal and a second terminal and a second write assist element (WA2) comprising a first terminal and a second terminal; and
the second terminal of the WA1 and the second terminal of the WA2 are coupled together to form a common node; and
a means for biasing the first terminal of the WA1;
a means for biasing the first terminal of the WA2; and
a means for voltage biasing the common node of the WA1 and the WA2, wherein the means for voltage biasing the common node comprises an amplifier configured to generate a common mode voltage, wherein the common mode voltage is different than a voltage potential of the storage medium.