Three-dimensional memory device including word line including polysilicon and metal
A 3D memory device and a method of manufacturing the same, the device including a substrate including a cell and an extension region; a cell stack including insulation layers and word lines alternately stacked on the substrate; channel structures vertically passing through the cell stack; a word line separation layer vertically passing through the cell stack and extending lengthwise in a first direction; a contact plug vertically connected to the word lines on the extension region; and a bit line extending lengthwise in a second direction on the channel structures, wherein each of the word lines includes an inner pattern including polysilicon; and an outer pattern including metal, the outer pattern surrounds an outer surface of the inner pattern, the channel structures vertically pass through the inner pattern, and the contact plug is on the outer pattern.
1. A three-dimensional (3D) memory device, comprising:
a substrate including a cell region and an extension region;
a cell stack including a plurality of insulation layers and a plurality of word lines alternately stacked on the substrate;
a plurality of channel structures vertically passing through the cell stack;
a word line separation layer vertically passing through the cell stack and extending lengthwise in a first direction parallel to a surface of the substrate;
a contact plug vertically connected to the plurality of word lines on the extension region; and
a bit line extending lengthwise in a second direction orthogonal to the first direction on the plurality of channel structures,
wherein:
each of the plurality of word lines includes:
an inner pattern including polysilicon; and
an outer pattern including metal,
the outer pattern surrounds an outer surface of the inner pattern,
the plurality of channel structures vertically pass through the inner pattern, and
the contact plug is on the outer pattern.
2. The 3D memory device as claimed in claim 1 , wherein an outer surface of the outer pattern contacts the word line separation layer.
3. The 3D memory device as claimed in claim 1 , wherein a portion of the outer pattern is between the inner pattern and the word line separation layer.
4. The 3D memory device as claimed in claim 1 , wherein the inner pattern surrounds the plurality of channel structures and fills a region between the plurality of channel structures.
5. The 3D memory device as claimed in claim 1 , wherein:
the polysilicon of the inner pattern is doped with P-type impurities, and
the outer pattern includes tungsten.
6. The 3D memory device as claimed in claim 1 , wherein the inner pattern is spaced apart from the word line separation layer.
7. The 3D memory device as claimed in claim 1 , wherein the inner pattern includes:
a cell inner pattern on the cell region; and
a plurality of dummy inner patterns on the extension region.
8. The 3D memory device as claimed in claim 7 , further comprising a plurality of dummy channel structures vertically passing through the cell stack on the extension region,
wherein the plurality of dummy inner patterns respectively surround the plurality of dummy channel structures.
9. The 3D memory device as claimed in claim 7 , wherein the cell inner pattern includes an outer surface having an uneven shape.
10. The 3D memory device as claimed in claim 7 , wherein the outer pattern includes a protrusion protruding toward the cell inner pattern.
11. The 3D memory device as claimed in claim 1 , wherein:
each of the plurality of word lines includes a string selection line at an uppermost level in the cell stack, and
the 3D memory device further comprises a string selection line separation pattern physically separating the string selection lines of each of the plurality of word lines.
12. The 3D memory device as claimed in claim 1 , wherein:
each of the plurality of channel structures includes:
a buried insulation pattern;
a channel pattern surrounding a side surface of the buried insulation pattern;
an information storage pattern surrounding a side surface of the channel pattern; and
a conductive pad on the buried insulation pattern, the channel pattern, and the information storage pattern, and
the information storage pattern contacts the inner pattern.
13. A three-dimensional (3D) memory device, comprising: a substrate including a cell region and an extension region; a cell stack including a plurality of insulation layers and a plurality of word lines, alternately stacked on the substrate, and having a staircase structure on the extension region; a plurality of cell channel structures vertically passing through the cell stack on the cell region; and a plurality of dummy channel structures vertically passing through the cell stack on the extension region, wherein: the plurality of word lines includes a plurality of inner patterns and a plurality of outer patterns surrounding outer surfaces of the plurality of inner patterns, the plurality of inner patterns on the cell region have an integrated plate shape, and the plurality of inner patterns on the extension region have a disk shape surrounding the plurality of dummy channel structures.
14. The 3D memory device as claimed in claim 13 , wherein:
the plurality of inner patterns includes polysilicon doped with P-type impurities, and
the plurality of outer patterns includes metal.
15. The 3D memory device as claimed in claim 13 , further comprising:
a word line separation layer vertically passing through the cell stack and extending lengthwise in a first direction parallel to a surface of the substrate; and
a contact plug vertically connected to the plurality of outer patterns on the extension region.
16. The 3D memory device as claimed in claim 15 , wherein the plurality of outer patterns contacts the word line separation layer.
17. The 3D memory device as claimed in claim 15 , wherein the plurality of inner patterns are apart from the word line separation layer.
18. A three-dimensional (3D) memory device, comprising:
a substrate including a cell region and an extension region;
a cell stack including a plurality of insulation layers and a plurality of word lines alternately stacked on the substrate;
a plurality of channel structures on the cell region to vertically pass through the cell stack;
a plurality of dummy channel structures on the extension region to vertically pass through the cell stack;
a word line separation layer vertically passing through the cell stack and extending lengthwise in a first direction parallel to a surface of the substrate;
a contact plug vertically connected to the plurality of word lines on the extension region; and
a bit line extending lengthwise in a second direction orthogonal to the first direction on the plurality of channel structures,
wherein:
each of the plurality of word lines includes a pad part arranged in a staircase structure on the extension region,
the pad part includes:
a plurality of dummy inner patterns each surrounding a portion of a sidewall of a corresponding dummy channel structure of the plurality of dummy channel structures; and
an outer pattern surrounding the plurality of dummy inner patterns,
in a plan view, the plurality of dummy inner patterns are apart from one another in the first direction and the second direction,
the outer pattern contacts the word line separation layer, and
the contact plug contacts the outer pattern.
19. The 3D memory device as claimed in claim 18 , wherein:
the plurality of dummy inner patterns each include polysilicon with P-type impurities doped thereon, and
the outer pattern includes metal.
20. The 3D memory device as claimed in claim 18 , wherein the plurality of dummy inner patterns are spaced apart from the word line separation layer.