Adaptive lower power state entry and exit

1. An apparatus comprising:

an upstream port to send information across a link;

power management circuitry to:

determine that an active state power management (ASPM) link state change condition is satisfied, and

change an APSM link state for the link based on the ASPM link state change condition being satisfied;

ASPM analysis logic to identify an event occurrence based on analyzing a last transaction layer packet (TLP) received prior to the ASPM link change condition being satisfied; and

ASPM tuning logic to tune the ASPM link state change condition based on identifying the occurrence of the event;

wherein the upstream port is to operate according to the ASPM link state.

2. The apparatus of claim 1 , the ASPM analysis logic to:

track a number of occurrences of the event; and

determine a correlation between the occurrences of the event and the ASPM link state change condition.

3. The apparatus of claim 2 , the ASPM tuning logic to tune the ASPM link state change condition based on the correlation between the occurrences of the event and the change in the ASPM link state.

4. The apparatus of claim 1 , wherein:

the power management circuitry to:

determine that an ASPM low power (L1) entry condition is satisfied, and

cause the link to enter an ASPM L1 link state;

the ASPM analysis logic to:

identify that the occurrence of the event corresponds to the entry into the ASPM L1 link state, and

correlate the occurrence of the event to the entry into the ASPM L1 link state; and

the ASPM tuning logic to tune the ASPM L1 entry condition based on the correlation between the occurrence of the event and the entry into the ASPM L1 link state.

5. The apparatus of claim 4 , wherein:

the ASPM L1 entry condition comprises an expiration of an idle timer;

the event comprises a receipt of a specific type of TLP in the last TLP; and

the ASPM tuning logic is to change the idle timer based on the correlation between the receipt of the specific type of TLP and the entry into the ASPM L1 link state.

6. The apparatus of claim 5 , wherein the ASPM tuning logic is to change the ASPM L1 entry condition to initiate ASPM L1 after receipt of the specific type of TLP.

7. The apparatus of claim 1 , wherein:

the power management circuitry is to:

determine that an ASPM low power (L1) exit condition is satisfied, and

cause the link to exit from an ASPM L1 link state;

the ASPM analysis logic is to:

identify that the occurrence of the event corresponds to the exit from the ASPM L1 link state, and

correlate the occurrence of the event to the exit from the ASPM L1 link state; and

the ASPM tuning logic is to:

tune the ASPM L1 exit condition based on the correlation between the occurrence of the event and the exit into the ASPM L1 link state.

8. A method comprising:

identifying an event occurrence based on analyzing a last transaction layer packet (TLP) received prior to an active state power management (ASPM) link state change;

correlating the event with the ASPM link state change;

tuning an ASPM link state change policy based on the correlation of the event with the ASPM link state change; and

changing an ASPM link state based on a subsequent occurrence of the event.

9. The method of claim 8 , further comprising:

tracking a number of occurrences of the event; and

determining a correlation between the occurrences of the event and the ASPM link state change.

10. The method of claim 9 , further comprising tuning the ASPM link state change policy based on the correlation between the occurrences of the event and the change in the ASPM link state.

11. The method of claim 8 , comprising:

determining that an ASPM low power (L1) entry condition is satisfied;

causing the link to enter an ASPM L1 link state;

identifying that occurrences of the event correspond to the entry into the ASPM L1 link state;

correlating the occurrences of the event to the entry into the ASPM L1 link state; and

tuning the ASPM L1 entry condition based on the correlation between the occurrence of the event and the entry into the ASPM L1 link state.

12. The method of claim 11 , wherein:

the ASPM L1 entry condition comprises an expiration of an idle timer; and

the method comprising:

receiving a specific type of TLP before entry into ASPM L1;

correlating occurrences of receipt of the specific type of TLP with entries into ASPM L1; and

changing ASPM L1 entry condition based on the correlation between the occurrences of the receipt of the specific type of TLP with entries into ASPM L1.

13. The method of claim 12 , wherein changing the ASPM L1 entry condition comprises shortening the idle timer.

14. The method of claim 12 , wherein changing the ASPM L1 entry condition comprises using the receipt of the specific type of TLP and subsequent acknowledgment of the receipt of a specific type of TLP to initiate ASPM L1 entry negotiation.

15. The method of claim 8 , further comprising:

tracking occurrences of the event after tuning the ASPM link state change policy;

determining that a traffic pattern has changed; and

refining the ASPM link state change policy based on the change in the traffic pattern.

16. The method of claim 8 , further comprising:

determining that an ASPM low power (L1) exit condition is satisfied;

initiating ASPM L1 exit negotiation;

correlating the event to the ASPM L1 exit condition being satisfied; and

tuning the ASPM L1 exit condition based on the correlation.

17. A system comprising:

a host device comprising a downstream port; and

an endpoint device comprising:

an upstream port coupled to the downstream port across a multilane link;

power management circuitry to:

determine that an active state power management (ASPM) link state change condition is satisfied, and

change the ASPM link state;

ASPM event analysis logic to:

identify an event occurrence based on analyzing a last transaction layer packet (TLP) received prior to the ASPM link state, and

determine a correlation between the occurrence of the event and the change in the ASPM link state; and

ASPM tuning logic to change the ASPM link state change condition based on the correlation between the occurrence of the event and the change in the ASPM link state;

the power management circuitry to send a request to change the ASPM link state to the downstream port across the multilane link;

wherein the downstream port is to accept or reject the request to change the ASPM link state.

18. The system of claim 17 , the ASPM event analysis logic to:

track a number of occurrences of the event; and

determine a correlation between the occurrences of the event and the change in the ASPM link state.

19. The system of claim 18 , the ASPM tuning logic to tune the ASPM link state change condition based on the correlation between the occurrences of the event and the change in the ASPM link state.

20. The system of claim 17 , wherein:

the power management circuitry is to:

determine that an ASPM low power (L1) entry condition is satisfied, and

cause the link to enter an ASPM L1 link state;

the ASPM event analysis logic to:

identify that the occurrence of the event corresponds to the entry into the ASPM L1 link state, and

correlate the occurrence of the event to the entry into the ASPM L1 link state; and

the ASPM tuning logic to tune the ASPM L1 entry condition based on the correlation between the occurrence of the event and the entry into the ASPM L1 link state.

21. The system of claim 20 , wherein:

the ASPM L1 entry condition comprises an expiration of an idle timer;

the event comprises a receipt of a specific type of TLP; and

the ASPM tuning logic to change the idle timer based on the correlation between the receipt of the specific TLP and the entry into the ASPM L1 link state.

22. The system of claim 21 , wherein the ASPM tuning logic is to change the ASPM L1 entry condition to initiate ASPM L1 after receipt of the specific TLP.

23. The system of claim 21 , wherein the ASPM tuning logic is to change the ASPM L1 entry condition to initiate ASPM L1 entry negotiation upon a transmission of an acknowledgment message following the specific TLP.

24. The system of claim 21 , wherein the ASPM tuning logic is to change the ASPM L1 entry condition by shortening the idle timer.

25. The system of claim 17 , wherein:

the power management circuitry is to:

determine that an ASPM low power (L1) exit condition is satisfied, and

cause the link to exit from an ASPM L1 link state;

the ASPM analysis logic is to:

identify that the occurrence of the event corresponds to the exit from the ASPM L1 link state, and

correlate the occurrence of the event to the exit from the ASPM L1 link state; and

the ASPM tuning logic is to tune the ASPM L1 exit condition based on the correlation between the occurrence of the event and the exit into the ASPM L1 link state.