Fin field-effect transistor device with low-dimensional material and method

1. A method comprising:

forming a dielectric fin protruding above a substrate;

forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer comprising a low dimensional material;

forming a gate structure over the channel layer;

forming metal source/drain regions on opposing sides of the gate structure;

forming a channel enhancement layer over the channel layer; and

forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

2. The method of claim 1 , wherein the low dimensional material comprises a two-dimensional semiconducting material, carbon nanotubes, or graphene nanoribbons.

3. The method of claim 2 , wherein the two-dimensional semiconducting material comprises MoS 2 , WS 2 , or WSe 2 .

4. The method of claim 1 , wherein forming the metal source/drain regions comprises:

selectively forming a self-assembled molecule (SAM) layer over an upper surface and sidewalls of the gate structure;

depositing a metal layer over the SAM layer and over the substrate;

attaching an adhesive tape over the deposited metal layer; and

peeling the adhesive tape off, wherein peeling the adhesive tape removes the SAM layer and an upper portion of the deposited metal layer, wherein a remaining portion of the deposited metal layer after the peeling forms the metal source/drain regions, wherein there is a gap between the gate structure and the metal source/drain regions after the peeling.

5. The method of claim 4 , further comprising adjusting a width of the gap between the gate structure and the metal source/drain regions by adjusting a length of molecules in the SAM layer.

6. The method of claim 5 , wherein the metal source/drain regions extend along second sidewalls of the dielectric fin.

7. The method of claim 6 , wherein the metal source/drain regions further extend along an upper surface of the channel layer distal from the substrate.

8. The method of claim 1 , wherein forming the channel enhancement layer comprises performing a plasma process to convert an upper layer of the channel layer into the channel enhancement layer.

9. The method of claim 1 , wherein forming the channel enhancement layer comprises applying a chemical solution to the channel layer to convert an upper layer of the channel layer into the channel enhancement layer.

10. The method of claim 1 , wherein forming the channel enhancement layer comprises depositing an oxide of the low dimensional material over the channel layer.

11. The method of claim 1 , further comprising:

forming openings in the passivation layer to expose the gate structure and the metal source/drain regions; and

forming contact plugs in the openings.

12. A method comprising:

forming a dielectric fin over a substrate;

forming a channel layer over the dielectric fin, the channel layer comprising low dimensional material;

forming a metal gate structure over the channel layer;

selectively forming a self-assembled molecule (SAM) layer over the metal gate structure;

depositing a metal material over the SAM layer and over the substrate;

attaching an adhesive tape to the metal material; and

peeling off the adhesive tape to remove the SAM layer and an upper layer of the metal material, wherein after peeling off the adhesive tape, a remaining portion of the metal material form source/drain regions on opposing sides of the metal gate structure.

13. The method of claim 12 , further comprising, after the peeling off, doping the channel layer to convert an upper layer of the channel layer into a channel enhancement layer.

14. The method of claim 13 , wherein doping the channel layer comprises doping the channel layer by performing a plasma process.

15. The method of claim 12 , wherein depositing the metal material comprises depositing a P-type metal material or an N-type metal material.

16. The method of claim 12 , wherein after the peeling off, there is a gap between the metal gate structure and the source/drain regions, wherein the method further comprises adjusting a molecule length of molecules in the SAM layer to adjust a width of the gap.

17. A method comprising:

forming a dielectric fin protruding above a substrate;

forming a channel layer that extends over an upper surface of the dielectric fin and along sidewalls of the dielectric fin, wherein the channel layer comprises a low dimensional material;

forming a gate structure over the channel layer;

forming a channel enhancement layer over the channel layer, wherein the channel enhancement layer is a doped layer of the channel layer; and

forming metal source/drain regions on opposing sides of the gate structure.

18. The method of claim 17 , wherein the low dimensional material comprises a two-dimensional semiconducting material, carbon nanotubes, or graphene nanoribbons.

19. The method of claim 18 , wherein the channel layer is formed to cover a first portion of the upper surface of the dielectric fin and expose a second portion of the upper surface of the dielectric fin, wherein a lower surface of the metal source/drain regions facing the substrate is formed to contact the second portion of the upper surface of the dielectric fin.

20. The method of claim 18 , wherein the channel enhancement layer comprises an oxide of the channel layer.