Snooping invalidation and snooping detection device and method

1. A system comprising a plurality of processing units interconnected by a network-on-chip network, wherein each of the plurality of processing units is coupled to a network interface configured to generate a plurality of flits, wherein the system further comprises:

a snooping invalidation logic circuit configured to perform a validation operation to detect and discard a duplicate flit header generated in the network interface,

wherein each of the plurality of flits are generated using an encoded key, the encoded key generated via XOR operators performed on: i) a counter associated with the flit, ii) a buffer index associated with the counter, and iii) a flit payload.

2. The system of claim 1 , wherein:

each flit of the plurality of flits are further generated with a table index identifying a location of the counter as stored in a validation table of the snooping invalidation logic circuit, wherein the encoded key and the table index are co-indexed in a buffer of the network interface, and

the buffer is indexable for each of the plurality of flits by the buffer index associated with a given counter, and wherein each indexable location of the buffer includes an instance of the encoded key and an instance of the table index for each counter, and

the snooping invalidation logic circuit, during the validation operation, is configured to detect the duplicated header flit by determining a mismatch between i) a given encoded key retrieved from a given header flit and ii) an encoded key retrieved from the buffer at an indexed location determined from the table index retrieved from the given header flit.

3. The system of claim 1 , wherein the validation operation to detect the duplicated header flit is performed in a single clock cycle of the each of the plurality of processing units.

4. The system of claim 1 , wherein the snooping invalidation logic circuit comprises a validation table, a comparator having a buffer length of the encoded key, and a decoding XOR operator having the buffer length of the encoded key.

5. The system of claim 4 , wherein the snooping invalidation logic circuit and associated validation table is lightweight employing an additional area of less than 5% to a baseline network interface configured to generate the same but lacking the snooping invalidation logic circuit and associated validation table.

6. The system of claim 1 , wherein the snooping invalidation logic circuit is configured to invalidate the duplicate flit header generated by a malicious hardware trojan embedded in the network interface using the encrypted key.

7. The system of claim 1 further comprising:

a snooping detection module comprising a mixed-analog and digital transistor circuit implemented at respective interfaces between each respective processing unit, or a substantial portion, of the plurality of processing units and a corresponding network interface associated with the respective processing unit,

wherein the mixed-analog and digital transistor circuit is configured to transition between a saturated state and a triode state based on a ratio between signals received and transmitted through the mixed-analog and digital transistor circuit,

wherein the snooping detection module is configured to compare the transition time from the triode state to the saturated state and a threshold time, and

wherein the snooping detection module is configured to generate, based the comparison, at its output, a notification signal to the respective processing unit or a monitoring circuit, wherein the notification signal indicates the respective processing unit as a source of a snooping attack in the system.

8. The system of claim 7 , wherein the snooping detection circuit comprises one or more MOS transistors configured to undergo stress-recovery periods in transitioning between ON and OFF operations that leads to threshold voltage (Vth) degradation of the one or more MOS transistors.

9. The system of claim 8 , wherein the snooping detection circuit further comprises a second set of one or more MOS transistors configured to undergo stress-recovery periods in transitioning between ON and OFF operations that leads to threshold voltage (Vth) degradation of the second set of one or more MOS transistors, and wherein operation of the one or more MOS transistors and the second set of one or more MOS transistors are selectable via inputs of the snooping detection circuit.

10. The system of claim 9 , wherein the snooping detection circuit uses the second set of one or more MOS transistors after the one or more MOS transistors has degraded from the threshold voltage (Vth) degradation.

11. The system of claim 10 , wherein the one or more MOS transistors comprise a PMOS or NMOS transistor.

12. The system of claim 1 , wherein the plurality of processing units collectively form a manycore chip comprising at least 64 cores.

13. The system of claim 12 , wherein the manycore chip comprises a multiprocessor system on chip (MPSoC) or chip multiprocessors (CMPs).

14. A method of operating the plurality of processing units interconnected by the network-on-chip network of claim 1 , wherein the method comprises:

generating the plurality of flits each comprising i) the encoded key, and ii) a table index identifying the location of the counter as stored in a validation table of the snooping invalidation logic circuit; and

detecting the duplicated header flit by determining a mismatch between i) the encoded key retrieved from each respective flit of the plurality of flits, and ii) an encoded key retrieved from a buffer at the indexed location determined from the table index.

15. The method of claim 14 , further comprising:

encoding the encoded key encoded from at least the counter associated with each respective flit.

16. The method of claim 14 , further comprising:

monitoring, via a snooping detection module, signals received and transmitted for a given processing unit configured with the snooping detection module,

wherein the snooping detection module comprises a mixed-analog and digital transistor circuit configured to transition between a saturated state and a triode state based on a ratio between the signals received and transmitted through the mixed-analog and digital transistor circuit, wherein the snooping detection module is configured to compare i) the transition time from the triode state to the saturated state and ii) a threshold time, and

wherein the snooping detection module is configured to generate, based the comparison, at its output, a notification signal to the respective processing unit or a monitoring circuit, wherein the notification signal indicates the respective processing unit as a source of a snooping attack in the system; and

generating the notification for the given processing unit when the resulting transition time for the snooping detection module exceeds the compared threshold time, wherein the notification provides an indication that the given processing unit is a source of a snooping attack.

17. The method of claim 16 , wherein the threshold time is configured so the notification is generated after 2 hours of the given processing unit performing a potential malicious task.

18. A system comprising a plurality of processing units interconnected by a network-on-chip communication, wherein each of the plurality of processing units is coupled to a network interface configured to generate a plurality of flits, wherein the system further comprises:

a snooping invalidation means for detecting and discarding a duplicate flit header generated in the network interface by a hardware trojan embedded in the network interface,

wherein each of the plurality of flits are generated using an encoded key, the encoded key generated via XOR operators performed on: i) a counter associated with the flit, ii) a buffer index associated with the counter, and iii) a flit payload.

19. The system of claim 18 further comprising:

a snooping detection means for detecting source within the system of snooping attacks, wherein the source comprises a hardware trojan embedded in the system.