Contact via formation

1. A semiconductor device, comprising:

an active region comprising a first channel region, a second channel region and a source/drain region disposed between the first channel region and the second channel region, the active region extending along a first direction;

a first gate structure disposed over the first channel region;

a second gate structure disposed over the second channel region; and

a source/drain contact structure over the source/drain region, the source/drain contact structure comprising:

a base portion extending lengthwise along a second direction perpendicular to the first direction, and

a via portion over the base portion, wherein the via portion tapers away from the base portion,

wherein the base portion is disposed between the first gate structure and the second gate structure along the second direction.

2. The semiconductor device of claim 1 , wherein the via portion comprises a taper angle between about 5° and about 60°.

3. The semiconductor device of claim 1 , wherein the via portion and the base portion are continuous and free of any intervening layer in between.

4. The semiconductor device of claim 1 ,

wherein the base portion comprises a first length along the second direction,

wherein the via portion comprises a second length along the second direction, and

wherein the second length is smaller than the first length.

5. The semiconductor device of claim 1 , further comprising:

a first dielectric layer over sidewalls of the via portion and top surfaces of the base portion; and

a second dielectric layer sandwiching the first dielectric layer and the base portion along the second direction,

wherein a composition of the first dielectric layer is different from a composition of the second dielectric layer.

6. The semiconductor device of claim 5 , further comprising:

a void in the second dielectric layer.

7. The semiconductor device of claim 5 , wherein the second dielectric layer partially extends into the base portion.

8. The semiconductor device of claim 5 , wherein a portion of the via portion rises above the second dielectric layer.

9. The semiconductor device of claim 5 , wherein the second dielectric layer is in direct contact with the sidewalls of the via portion and the top surfaces of the base portion.

10. A semiconductor device, comprising:

a first gate structure sandwiched between a first gate spacer and a second gate spacer, the first gate structure extending lengthwise along a first direction;

a first gate self-aligned contact (SAC) dielectric feature over the first gate structure, the first gate spacer and the second gate spacer;

a second gate structure sandwiched between a third gate spacer and a fourth gate spacer, the first gate structure extending lengthwise along the first direction;

a second gate SAC dielectric feature over the second gate structure, the third gate spacer, and the fourth gate spacer; and

a source/drain contact structure comprises a base portion disposed between the second gate spacer and the third gate spacer and a via portion disposed between the first gate SAC dielectric feature and the second gate SAC dielectric feature,

wherein the via portion tapers away from the base portion.

11. The semiconductor device of claim 10 , wherein the via portion and the base portion are continuous and free of any intervening layer in between.

12. The semiconductor device of claim 10 ,

wherein the base portion comprises a first length along a second direction perpendicular to the first direction,

wherein the via portion comprises a second length along the second direction, and

wherein the second length is smaller than the first length.

13. The semiconductor device of claim 10 , further comprising:

a liner disposed over sidewalls of the via portion and top surfaces of the base portion; and

a dielectric layer disposed over the liner.

14. The semiconductor device of claim 13 , wherein the dielectric layer comprises a void.

15. The semiconductor device of claim 13 , wherein the liner comprises titanium nitride, tantalum nitride, or titanium silicide nitride.

16. A method, comprising:

providing a conductive feature disposed in a first dielectric layer;

forming a patterned hard mask layer over the conductive feature and the first dielectric layer; and

etching the conductive feature using the patterned hard mask as an etch mask to form a via portion and a base portion out of the conductive feature,

wherein the base portion comprises a first width and the via portion comprises a second width along a direction,

wherein the first width is greater than the second width.

17. The method of claim 16 , wherein the conductive feature is disposed over a source/drain feature of a transistor.

18. The method of claim 16 , further comprising:

depositing a second dielectric layer over the via portion, the patterned hard mask, the base portion and the first dielectric layer; and

performing a planarization process to remove the patterned hard mask such that top surfaces of the first dielectric layer, the second dielectric layer, and via portion are coplanar.

19. The method of claim 16 , further comprising:

selectively removing the patterned hard mask;

depositing a second dielectric layer over the via portion, the base portion and the first dielectric layer; and

performing a planarization process such that top surfaces of the first dielectric layer, the second dielectric layer, and via portion are coplanar.

20. The method of claim 16 ,

wherein the etching of the conductive feature comprises forming a first recess and a second recess in the conductive feature, and

wherein the via portion is defined by the first recess and the second recess.