Matrix operation optimization mechanism
An apparatus to facilitate machine learning matrix processing is disclosed. The apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters and a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.
1. An apparatus to facilitate machine learning matrix processing, comprising:
a memory to store matrix data;
one or more processors to execute an instruction to:
examine a message descriptor included in the instruction to determine a first of a plurality of types of matrix layout manipulation operations that is to be executed;
examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, wherein the parameters comprise an array length attribute indicating a quantity of 2D memory blocks to retrieve from memory;
retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters; and
a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.
2. The apparatus of claim 1 , wherein the plurality of parameters further comprise an indication of a 2D block size.
3. The apparatus of claim 2 , wherein the plurality of parameters further comprises attributes defining a width, height and pitch of each of the one or more blocks.
4. The apparatus of claim 3 , wherein the message descriptor indicates that a 2D block read with transpose operation is to be executed.
5. The apparatus of claim 4 , wherein the one or more processors perform a transpose operation on each of the one or more blocks of the matrix data and stores the transposed matrix in the first set of registers.
6. The apparatus of claim 3 , wherein the message descriptor indicates that a 2D block read with transform operation is to be executed.
7. The apparatus of claim 6 , wherein the one or more processors perform a transform operation on each of the one or more blocks of the matrix data and stores the transformed matrix in the first set of registers.
8. The apparatus of claim 3 , wherein the message descriptor indicates that a 2D block read with transpose and transform operation is to be executed.
9. A method to facilitate machine learning matrix processing, comprising:
examining a message descriptor included in the instruction to determine a first of a plurality of types of matrix layout manipulation operations that is to be executed;
examining a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, wherein the parameters comprise an array length attribute indicating a quantity of 2D memory blocks to retrieve from memory;
retrieving one or more blocks of matrix data from memory based on the plurality of parameters; and
storing the one or more blocks of the matrix data a first set of a plurality of registers.
10. The method of claim 9 , wherein the plurality of parameters further comprise an indication of a 2D block size.
11. The method of claim 10 , wherein the plurality of parameters further comprises attributes defining a width, height and pitch of each of the one or more blocks.
12. The method of claim 11 , wherein the message descriptor indicates that a 2D block read with transform operation is to be executed.
13. The method of claim 12 , wherein the transform operation comprises:
performing a transform operation on each of the one or more blocks of the matrix data; and
storing the transformed matrix in the first set of registers.
14. The method of claim 9 , wherein the message descriptor indicates that a 2D block read with transpose operation is to be executed.
15. The method of claim 14 , wherein the transpose operation comprises:
performing a transpose operation on each of the one or more blocks of the matrix data; and
storing the transposed matrix in the first set of registers.
16. At least one non-transitory computer readable medium having instructions stored thereon, which when executed by one or more processors, cause the processors to:
examine a message descriptor included in the instruction to determine a first of a plurality of types of matrix layout manipulation operations that is to be executed;
examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, wherein the parameters comprise an array length attribute indicating a quantity of 2D memory blocks to retrieve from memory;
retrieve one or more blocks of matrix data from memory based on the plurality of parameters; and
store the one or more blocks of the matrix data a first set of a plurality of registers.
17. The computer readable medium of claim 16 , wherein the plurality of parameters further comprise an indication of a 2D block size.
18. The computer readable medium of claim 17 , wherein the plurality of parameters further comprises attributes defining a width, height and pitch of each of the one or more blocks.
19. The computer readable medium of claim 18 , wherein the message descriptor indicates that a 2D block read with transpose operation is to be executed.
20. The computer readable medium of claim 18 , wherein the message descriptor indicates that a 2D block read with transform operation is to be executed.