IP Library › Granted Patent US 11,250,910
Granted Patent B2
US 11,250,910 · App. 16/891,028 · Granted Feb 15, 2022

Control method and controller of a programming process for 3D NAND flash

Inventors: Ying Huang (Wuhan, CN); Hongtao Liu (Wuhan, CN); Qiguang Wang (Wuhan, CN); Wenzhe Wei (Wuhan, CN)
Assignee: Yangtze Memory Technologies Co., Ltd.
G11C16/0483G11C16/10G11C16/26G11C16/3459G11C11/5671
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Quick Facts
Patent No.
US 11,250,910
App. No.
16/891,028
Granted
Feb 15, 2022
Kind
B2
Abstract

A control method of a programming process for a three-dimensional (3D) NAND flash memory array comprises programming a bit-cell of the 3D NAND flash memory array in a programming stage; and verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage; wherein the programming stage comprises programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses; wherein the verification stage comprises reading the bit-cell of the 3D NAND flash memory array with lower or higher voltage than normal reading voltage pulse.

Claims (88)

1. A control method of a programming process for a three-dimensional (3D) NAND flash memory array, comprising:

programming a bit-cell of the 3D NAND flash memory array in a programming stage; and

verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage;

wherein the programming stage comprises:

programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses;

wherein in the programming stage, a voltage and a pulse width of each of the plurality of programming voltage pulses are programmable;

wherein pulse widths of the plurality of programming voltage pulses are incremental;

wherein the verification stage comprises:

reading the bit-cell of the 3D NAND flash memory array with a voltage lower or higher than a normal reading voltage pulse.

2. The control method of claim 1 , wherein voltages of the plurality of programming voltage pulses are incremental.

3. The control method of claim 1 , wherein voltages of the plurality of programming voltage pulses are decremental.

4. The control method of claim 1 , wherein voltages of a part of the plurality of programming voltage pulses are incremental.

5. The control method of claim 1 , wherein voltages of a part of the plurality of programming voltage pulses are decremental.

6. A control method of a programming process for a three-dimensional (3D) NAND flash memory array, comprising:

programming a bit-cell of the 3D NAND flash memory array in a programming stage; and

verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage;

wherein the programming stage comprises:

programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses;

wherein in the programming stage, a voltage and a pulse width of each of the plurality of programming voltage pulses are programmable;

wherein pulse widths of the plurality of programming voltage pulses are decremental;

wherein the verification stage comprises:

reading the bit-cell of the 3D NAND flash memory array with a voltage lower or higher than a normal reading voltage pulse.

7. A control method of a programming process for a three-dimensional (3D) NAND flash memory array, comprising:

programming a bit-cell of the 3D NAND flash memory array in a programming stage; and

verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage;

wherein the programming stage comprises:

programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses;

wherein in the programming stage, a voltage and a pulse width of each of the plurality of programming voltage pulses are programmable;

wherein pulse widths of a part of the plurality of programming voltage pulses are incremental;

wherein the verification stage comprises:

reading the bit-cell of the 3D NAND flash memory array with a voltage lower or higher than a normal reading voltage pulse.

8. A control method of a programming process for a three-dimensional (3D) NAND flash memory array, comprising:

programming a bit-cell of the 3D NAND flash memory array in a programming stage; and

verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage;

wherein the programming stage comprises:

programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses;

wherein in the programming stage, a voltage and a pulse width of each of the plurality of programming voltage pulses are programmable;

wherein pulse widths of a part of the plurality of programming voltage pulses are decremental;

wherein the verification stage comprises:

reading the bit-cell of the 3D NAND flash memory array with a voltage lower or higher than a normal reading voltage pulse.

9. A controller for a programming process for a three-dimensional (3D) NAND flash memory array, comprising:

a storage unit, configured to store a program code; and

a processing unit, configured to perform the following steps:

programming a bit-cell of the 3D NAND flash memory array in a programming stage; and

verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage;

wherein the programming stage comprises:

programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses;

wherein in the programming stage, a voltage and a pulse width of each of the plurality of programming voltage pulses are programmable;

wherein pulse widths of the plurality of programming voltage pulses are incremental;

wherein the verification stage comprises:

reading the bit-cell of the 3D NAND flash memory array with a voltage lower or higher than a normal reading voltage pulse.

10. The controller for claim 9 , wherein voltages of the plurality of programming voltage pulses are incremental.

11. The controller of claim 9 , wherein voltages of the plurality of programming voltage pulses are decremental.

12. The controller of claim 9 , wherein voltages of a part of the plurality of programming voltage pulses are incremental.

13. The controller of claim 9 , wherein voltages of a part of the plurality of programming voltage pulses are decremental.

14. A controller for a programming process for a three-dimensional (3D) NAND flash memory array, comprising:

a storage unit, configured to store a program code; and

a processing unit, configured to perform the following steps:

programming a bit-cell of the 3D NAND flash memory array in a programming stage; and

verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage;

wherein the programming stage comprises:

programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses;

wherein in the programming stage, a voltage and a pulse width of each of the plurality of programming voltage pulses are programmable;

wherein pulse widths of the plurality of programming voltage pulses are decremental;

wherein the verification stage comprises:

reading the bit-cell of the 3D NAND flash memory array with a voltage lower or higher than a normal reading voltage pulse.

15. A controller for a programming process for a three-dimensional (3D) NAND flash memory array, comprising:

a storage unit, configured to store a program code; and

a processing unit, configured to perform the following steps:

programming a bit-cell of the 3D NAND flash memory array in a programming stage; and

verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage;

wherein the programming stage comprises:

programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses;

wherein in the programming stage, a voltage and a pulse width of each of the plurality of programming voltage pulses are programmable;

wherein pulse widths of a part of the plurality of programming voltage pulses are incremental;

wherein the verification stage comprises:

reading the bit-cell of the 3D NAND flash memory array with a voltage lower or higher than a normal reading voltage pulse.

16. A controller for a programming process for a three-dimensional (3D) NAND flash memory array, comprising:

a storage unit, configured to store a program code; and

a processing unit, configured to perform the following steps:

programming a bit-cell of the 3D NAND flash memory array in a programming stage; and

verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage;

wherein the programming stage comprises:

programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses;

wherein in the programming stage, a voltage and a pulse width of each of the plurality of programming voltage pulses are programmable;

wherein pulse widths of a part of the plurality of programming voltage pulses are decremental;

wherein the verification stage comprises:

reading the bit-cell of the 3D NAND flash memory array with a voltage lower or higher than a normal reading voltage pulse.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2020
From: HUANG, YING; LIU, HONGTAO; WANG, QIGUANG; WEI, WENZHE
To: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Reel/Frame 052817/0770 →
Continuity (2)
Continuation PCTCN2020088769 · May 6, 2020
Related Publication 20210350853A1 · Nov 11, 2021