Non-volatile memory based processors and dataflow techniques

1. A compute chip comprising:

a plurality of compute circuitry of a monolithic integrated circuit, wherein the plurality of compute circuitry perform computation operations;

one or more non-volatile memory circuits of the monolithic integrated circuit;

one or more communication interfaces of the monolithic integrated circuit configured to communicatively couple one or more circuits of the monolithic integrated circuit to one or more circuits external to the monolithic integrated circuit; and

one or more communication channels of the monolithic integrated circuit configurable to communicatively couple the plurality of compute circuitry, the one or more non-volatile memory circuits and the one or more communication interface together, wherein results of one or more computations performed by one or more of the compute circuitry is passed as operands to one or more other of the plurality of compute circuitry to perform one or more other computations without the results of the one or more computations being written to the one or more non-volatile memory circuits.

2. The compute chip of claim 1 , wherein the one or more non-volatile memory circuits includes memory selected from the group consisting of resistive random-access memory (ROAM), magnetic random-access memory (MRAM), Flash memory (FLASH), and phase change random access memory (PCRAM).

3. The compute chip of claim 1 , wherein the plurality of compute circuitry are configurable to perform computation operations of a compute model.

4. The compute chip of claim 3 , wherein the one or more non-volatile memory circuitry are configurable to store respective set of weights or kernel functions for computation operations performed by the respective one or more compute circuitry based on the compute model.

5. The compute chip of claim 4 , wherein respective ones of the plurality of processing elements includes a respective compute circuitry and a respective non-volatile memory circuitry.

6. The compute chip of claim 5 , wherein the one or more communication channels are further configurable to communicatively couple the respective compute circuitry of the plurality of processing elements together in parallel and in series based on the compute model.

7. A processor comprising:

a plurality of processing elements of a monolithic integrated circuit, wherein;

each processing element includes a processing circuitry and a non-volatile memory circuitry;

the compute circuitry of respective processing elements are configurable to perform a respective computation;

the non-volatile memory circuitry of respective processing elements are configurable to store a respective set of weights or kernel functions; and

the plurality of processing elements are configurable to pass data between processing elements, wherein results of one or more computations performed by one or more of the compute circuitry passes as operands to one or more other of the compute circuitry to perform one or more other computations without the results of the one or more computations being written to the one or more non-volatile memory circuits.

8. The processor of claim 7 , wherein the plurality of processing elements include processors selected from the group consisting of central processing units (CPU), graphics processing units (GPU), tensor processing units (TPU), artificial intelligence (AI) accelerators, and memory processing units.

9. The processor of claim 7 , wherein the non-volatile memory circuitry includes memory selected from the group consisting of resistive random-access memory (ReRAM), magnetic random-access memory (MRAM), Flash memory (FLASH), and phase change random access memory (PCRAM).

10. The processor of claim 7 , wherein the compute circuitry of the plurality of processing elements are configurable to perform respective computation operations of a compute model.

11. The of claim 10 , wherein the compute circuitry of the plurality of processing elements are configurable to pass the data between processing elements based on computation operations of the compute model.

12. The processor of claim 11 , wherein the non-volatile memory circuitry of the plurality of processing elements are configurable to store the respective set of weights or kernel functions based of the compute model.

13. The processor of claim 12 , further comprising:

data links configurable to couple the plurality of processing elements based on edges of the compute model.

14. A processor configuration method comprising:

receiving a compute model including a plurality of nodes, edges coupling various ones of the plurality of nodes together, and weights of respective nodes;

configuring compute circuitry of a plurality of processing elements based on respective ones of the plurality of nodes;

configuring data flow between the configured processing elements based on the edges, wherein results of one or more computations performed by one or more of the compute circuitry is passed as operands to one or more other of the compute circuitry to perform one or more other computations without the results of the one or more computations being written to non-volatile memory circuitry; and

loading the weights of respective nodes into the non-volatile memory circuitry of respective processing elements.

15. The processor configuration method according to claim 14 , further comprising:

executing the compute model on the configured compute elements in response to one or more inputs to generate one or more outputs.

16. The processor configuration method according to claim 14 , wherein the processing elements include on-chip processors selected from the group consisting of central processing units (CPU), graphics processing units (GPU), tensor processing units (TPU), artificial intelligence (AI) accelerators, and memory processing units.

17. The processor configuration method according to claim 14 , wherein the non-volatile memory circuitry includes on-chip memory selected from the group consisting of resistive random-access memory (ReRAM), magnetic random-access memory (MRAM), Flash memory (FLASH), and phase change random access memory (PCRAM).

18. The processor configuration method according to claim 15 , further comprising reading in the one or more input from off-chip memory.

19. The processor configuration method according to claim 18 , further comprising writing the one or more output to the off-chip memory.

20. The processor configuration method according to claim 14 , wherein configuring the data flow between the configured processing elements based on the edges includes configuring data links between the plurality of processing elements based on the edges of the compute model.