IP Library › Granted Patent US 11,462,574
Granted Patent B2
US 11,462,574 · App. 16/896,146 · Granted Oct 4, 2022

Display substrate, method of manufacturing the same, and display device including the same

Inventors: Sungwon Cho (Hwaseong-si, KR); Yu-Gwang Jeong (Anyang-si, KR); Daewon Choi (Cheonan-si, KR); Seon-Il Kim (Hwaseong-si, KR); Subin Bae (Hwaseong-si, KR); Yun Jong Yeo (Hwaseong-si, KR)
Assignee: Samsung Display Co., Ltd.
H01L27/1255H01L27/124H01L27/1259H01L29/78648
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Quick Facts
Patent No.
US 11,462,574
App. No.
16/896,146
Granted
Oct 4, 2022
Kind
B2
Abstract

A display substrate includes a substrate, a first gate electrode on the substrate, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, a second gate electrode on the second gate insulating layer, an interlayer insulating layer on the second gate electrode, a first electrode on the interlayer insulating layer to contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer, and a second electrode on the interlayer insulating layer to contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

Claims (51)

1. A display substrate comprising:

a substrate;

a first gate electrode on the substrate;

a first gate insulating layer on the substrate to cover the first gate electrode;

an active layer on the first gate insulating layer;

a second gate insulating layer on the first gate insulating layer to cover the active layer;

a second gate electrode on the second gate insulating layer;

an interlayer insulating layer on the second gate insulating layer to cover the second gate electrode;

a first electrode on the interlayer insulating layer to directly contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer; and

a second electrode on the interlayer insulating layer to directly contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer,

wherein the first gate insulating layer comprises:

a first sub-insulating layer on the substrate to cover the first gate electrode; and

a second sub-insulating layer on the first sub-insulating layer, the second sub-insulating layer being different in material from the first sub-insulating layer, and

wherein the second contact hole extends through the first sub-insulating layer and the second sub-insulating layer.

2. The display substrate of claim 1 , wherein the second electrode directly contacts a top surface of the first gate electrode via the second contact hole.

3. The display substrate of claim 1 , wherein the first contact hole comprises:

a first portion formed through the second gate insulating layer to expose the top surface of the active layer;

a second portion formed through the active layer to expose the side wall of the active layer; and

a third portion formed through the portion of the first gate insulating layer to expose the bottom surface of the active layer.

4. The display substrate of claim 3 , wherein a width of the first portion is greater than a width of the second portion.

5. The display substrate of claim 3 , wherein a width of the third portion is greater than a width of the second portion.

6. The display substrate of claim 1 , wherein the portion of the first gate insulating layer is a portion of the second sub-insulating layer.

7. The display substrate of claim 1 , wherein the first sub-insulating layer comprises silicon nitride.

8. The display substrate of claim 1 , wherein the second sub-insulating layer comprises silicon oxide.

9. The display substrate of claim 1 , wherein the active layer comprises polycrystalline silicon.

10. The display substrate of claim 1 , wherein the second gate insulating layer comprises silicon oxide.

11. The display substrate of claim 1 , wherein the first gate electrode overlaps the second gate electrode with the active layer interposed therebetween.

12. The display substrate of claim 1 , wherein the interlayer insulating layer comprises:

a first interlayer insulating layer on the second gate insulating layer to cover the second gate electrode; and

a second interlayer insulating layer on the first interlayer insulating layer.

13. The display substrate of claim 12 , wherein the first interlayer insulating layer comprises silicon nitride.

14. The display substrate of claim 12 , further comprising a capacitor electrode between the first interlayer insulating layer and the second interlayer insulating layer, and overlapping the second gate electrode.

15. The display substrate of claim 1 , wherein a top surface of the first electrode and a top surface of the second electrode are coplanar.

16. A display device comprising:

a substrate;

a first gate electrode on the substrate;

a first gate insulating layer on the substrate to cover the first gate electrode;

an active layer on the first gate insulating layer;

a second gate insulating layer on the first gate insulating layer to cover the active layer;

a second gate electrode on the second gate insulating layer;

an interlayer insulating layer on the second gate insulating layer to cover the second gate electrode;

a first electrode on the interlayer insulating layer to directly contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer;

a second electrode on the interlayer insulating layer to directly contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer;

a planarization layer on the interlayer insulating layer to cover the first electrode and the second electrode;

a pixel electrode on the planarization layer;

a counter electrode overlapping the pixel electrode; and

a light emitting layer between the pixel electrode and the counter electrode,

wherein the first gate insulating layer comprises:

a first sub-insulating layer on the substrate to cover the first gate electrode; and

a second sub-insulating layer on the first sub-insulating layer, the second sub-insulating layer being different in material from the first sub-insulating layer, and

wherein the second contact hole extends through the first sub-insulating layer and the second sub-insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2020
From: CHO, SUNGWON; JEONG, YU-GWANG; CHOI, DAEWON; KIM, SEON-IL; BAE, SUBIN; YEO, YUN JONG
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 052879/0435 →
Priority Claims (1)
KR 10-2019-0125992 · Oct 11, 2019 · national
Continuity (1)
Related Publication 20210111198A1 · Apr 15, 2021