Memory device having word line groups and operating method of the memory device

1. A memory device comprising:

a first stack including first memory cells that are vertically stacked on a substrate;

a second stack, over the first stack, including second memory cells, wherein a width of a memory cell located at a lowest portion of the second stack is narrower than a width of a memory cell located at a highest portion of the first stack;

word lines, wherein each of the first memory cells and the second memory cells is coupled to a corresponding word line;

a group controller configured to:

group the word lines into word line groups separated by a boundary region, which is set to an interlayer between the first stack and the second stack;

perform a test operation on memory cells adjacent to the boundary region by checking at least one of a program speed of the memory cells, an erase speed of the memory cells, and a period in which a threshold voltage is maintained after the memory cells are programmed;

determine whether to set a new interlayer as the boundary region based on a result of the test operation; and

when it is determined to set the new interlayer as the boundary region, determine the new interlayer and set the new interlayer as the boundary region before a program operation is performed; and

a voltage generator configured to store, in a voltage table, voltage values of operating voltages to be respectively applied to the word lines included in each of the word line groups,

wherein the group controller is configured to determine the voltage values depending on a position of the boundary region changed by the group controller.

2. The memory device of claim 1 , wherein the group controller is configured to group the word line groups into at least two groups according to electrical characteristics of portions of the first and second memory cells adjacent to the boundary region.

3. The memory device of claim 1 , wherein the group controller is configured to set a test region including portions of the first and second memory cells adjacent to the boundary region between the word line groups before the test operation is performed.

4. The memory device of claim 3 , wherein the word lines adjacent to upper and lower portions with respect to the boundary region are included in the test region.

5. The memory device of claim 3 , wherein the group controller is configured to change the position of the boundary region such that memory cells having similar electrical characteristics among the first and second memory cells adjacent to the boundary region included in the test region and connected to different word lines are included in the same group.

6. The memory device of claim 1 , wherein the voltage values stored in the voltage table are level values of the operating voltages used in a program, read, or erase operation.

7. The memory device of claim 6 , wherein the voltage values are respectively set with respect to the word line groups, based on the boundary region.

8. The memory device of claim 6 , wherein the voltage generator is configured to:

primarily set the voltage values according to a structural difference of the first and second stacks; and

secondarily set the voltage values according to the result of the test operation.

9. The memory device of claim 8 , wherein the voltage values changed depending on the result of the test operation are included in the voltage table.

10. A method for operating a memory device, the method comprising:

determining a first boundary region between a first stack and a second stack, wherein the second stack is over the first stack, and a width of a memory cell located at a lowest portion of the second stack is narrower than a width of a memory cell located at a highest portion of the first stack;

setting voltages corresponding to each of word line groups to a first voltage value;

performing a test operation on memory cells adjacent to the first boundary region by checking at least one of a program speed of the memory cells, an erase speed of the memory cells, and a period in which a threshold voltage is maintained after the memory cells are programmed;

changing the first boundary region to a second boundary region, depending on a result of the test operation;

changing the first voltage value to a second voltage value depending on the second boundary region; and

performing a program operation on a selected memory cell in one of the first or second stack using the voltages corresponding to the second voltage value.

11. The method of claim 10 , wherein the second voltage value includes different final voltage values set with respect to the word line groups having different electrical characteristics of memory cells in the first and second stacks.

12. The method of claim 10 , further comprising setting a test region with respect to the first boundary region before the first boundary region is changed.

13. The method of claim 12 , wherein the test region includes a plurality of word lines sequentially adjacent to the first boundary region.

14. The method of claim 12 , wherein the test region includes word lines adjacent to upper and lower portions of the first boundary region.

15. A method for operating a memory device, the method comprising:

setting a first boundary region dividing memory cells into first and second groups, wherein the first group is included in a first stack and the second group is included in a second stack that is over the first stack;

performing a test operation on memory cells adjacent to the first boundary region by checking at least one of a program speed of the memory cells, an erase speed of the memory cells, and a period in which a threshold voltage is maintained after the memory cells are programmed;

changing the first boundary region to a second boundary region by changing a position of the first boundary region, based on a result of the test operation; and

performing a program operation on the memory cells using voltages set according to the second boundary region.

16. The method of 15 , wherein the first and second groups are reset such that memory cells having similar electrical characteristics are included in the same group based on the result of the test operation.

17. A memory device comprising:

a first stack including first memory cells that are vertically stacked on a substrate;

a second stack, over the first stack, including second memory cells, wherein a width of a memory cell located at a lowest portion of the second stack is narrower than a width of a memory cell located at a highest portion of the first stack;

a third stack, over the second stack, including third memory cells, wherein a width of a memory cell located at a lowest portion of the third stack is narrower than a width of a memory cell located at a highest portion of the second stack;

word lines, wherein each of the first memory cells, the second memory cells and the third memory cells is coupled to a corresponding word line;

a group controller configured to:

group the word lines into word line groups separated by a first boundary region between the first and second stacks and a second boundary region between the second and third stacks;

perform a test operation on memory cells adjacent to the first and second boundary regions by checking at least one of a program speed of the memory cells, an erase speed of the memory cells, and a period in which a threshold voltage is maintained after the memory cells are programmed; and

determine whether to set new boundary regions based on a result of the test operation; and

a voltage generator configured to store, in a voltage table, voltage values of operating voltages to be respectively applied to the word lines included in each of the word line groups,

wherein the group controller is configured to determine the voltage values depending on a position of the new boundary regions.

18. The memory device of claim 17 , wherein the group controller is configured to set test regions including portions of the first and second memory cells adjacent to the first boundary region and portions of the second and third memory cells adjacent to the second boundary region before the test operation is performed.

19. The memory device of claim 18 , wherein the group controller is configured to change positions of the first and second boundary regions such that memory cells having similar electrical characteristics among the first and second memory cells adjacent to the first boundary region are included in the same group, and memory cells having similar electrical characteristics among the second and third memory cells adjacent to the second boundary region are included in the same group.