IC package with multiple dies

1. An integrated circuit (IC) package comprising:

a first die with a first surface overlaying a substrate, wherein the first die comprises a first metal pad at a second surface opposing the first surface;

a dielectric layer having a first surface contacting the second surface of the first die; and

a second die with a first surface that contacts a second surface of the dielectric layer, the second die comprising a second metal pad at the first surface and aligned with the first metal pad of the first die, wherein a plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad, wherein the second die further comprises a third metal pad at a second surface of the second die opposite the first surface of the second die.

2. The IC package of claim 1 , wherein the first metal pad and the second metal pad form a capacitor and the first die and the second die communicate through the capacitor.

3. The IC package of claim 2 , wherein the first die and the second die are galvanically isolated.

4. The IC package of claim 3 , wherein the first die has a first ground potential and the second die has a second ground potential, wherein the first ground potential differs from the second ground potential by at least 40 volts.

5. The IC package of claim 1 , wherein the surface of the second die is a first surface, and the substrate is a first substrate, the IC package further comprising:

a second substrate contacting a second surface of the second die, wherein the second surface of the second die opposes the first surface of the second die.

6. The IC package of claim 1 , wherein the dielectric layer comprises:

a first protective overcoat that contacts the second surface of the first die;

a second protective overcoat that contacts the surface of the second die; and

a non-conductive die adhesive sandwiched between the first protective overcoat and the second protective overcoat.

7. The IC package of claim 6 , further comprising:

a recess in the first protective overcoat that exposes a fourth metal pad formed at the second surface of the first die; and

a wire bond coupled to the third metal pad.

8. An integrated circuit (IC) package, comprising:

a first die with a first surface overlaying a substrate, wherein the first die comprises a first metal pad at a second surface opposing the first surface;

a dielectric layer having a first surface contacting the second surface of the first die;

a second die with a surface that contacts a second surface of the dielectric layer, the second die comprising a second metal pad aligned with the first metal pad of the first die, wherein a plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad, wherein the surface of the second die is a first surface, and the substrate is a first substrate;

a second substrate contacting a second surface of the second die, wherein the second surface of the second die opposes the first surface of the second die;

a recess in the second substrate and an insulating layer of the second die that exposes a portion of a metal layer of the second die to provide a third metal pad, wherein the insulating layer of the second die separates the metal layer of the second die from the second substrate; and

a wire bond coupled to the third metal pad.

9. The IC package of claim 8 , wherein the second die has a smaller footprint than the first die.

10. An integrated circuit (IC) package, comprising:

a first die with a first surface overlaying a first substrate, wherein the first die comprises a first metal pad at a second surface opposing the first surface;

a dielectric layer having a first surface contacting the second surface of the first die, wherein the dielectric layer comprises:

a first protective overcoat that contacts the second surface of the first die;

a second protective overcoat that contacts the surface of the second die; and

a non-conductive die adhesive sandwiched between the first protective overcoat and the second protective overcoat;

a second die with a first surface that contacts a second surface of the dielectric layer, the second die comprising a second metal pad aligned with the first metal pad of the first die, wherein a plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad;

a second substrate contacting a second surface of the second die, wherein the second surface of the second die opposes the first surface of the second die;

a first recess in the second substrate and an insulating layer of the second die that exposes a portion of a metal layer in the second die to provide a third metal pad, wherein the insulating layer of the second die separates the metal layer of the second die from the second substrate;

a first wire bond coupled to the third metal pad;

a second recess in the first protective overcoat that exposes a fourth metal pad formed at the second surface of the first die; and

a second wire bond coupled to the fourth metal pad.

11. The IC package of claim 10 , wherein the second die has a smaller footprint than the first die.

12. The IC package of claim 10 , wherein the first die and the second die are galvanically isolated.

13. An integrated circuit (IC) package, comprising:

a first die with a first surface overlaying a substrate, wherein the first die comprises a first metal pad at a second surface opposing the first surface;

a dielectric layer having a first surface contacting the second surface of the first die, wherein the dielectric layer comprises:

a first protective overcoat that contacts the second surface of the first die;

a second protective overcoat that contacts the surface of the second die;

a spacer plate sandwiched between the first protective overcoat and the second protective overcoat;

a recess in the first protective overcoat that exposes a third metal pad formed at the second surface of the first die;

a first non-conductive die adhesive (NCDA) layer sandwiched between the first protective overcoat and a first surface of the spacer plate, wherein the first NCDA layer overlays a portion of the first protective overcoat that is spaced apart from the recess in the first protective overcoat; and

a second NCDA layer sandwiched between the second protective overcoat and a second surface of the spacer plate that opposes the first surface of the spacer plate; and

a second die with a surface that contacts a second surface of the dielectric layer, the second die comprising a second metal pad aligned with the first metal pad of the first die, wherein a plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.

14. The IC package of claim 13 , wherein the surface of the second die is a first surface and the substrate is a first substrate, the IC package further comprising:

a second substrate contacting a second surface of the second die, wherein the second surface of the second die opposes the first surface of the second die;

a first recess in the second substrate and an insulating layer of the second die that exposes a metal layer of the second die to provide a third metal pad, wherein the insulating layer of the second die separates the metal layer of the second die from the second substrate;

a first wire bond coupled to the third metal pad;

a second recess in the first protective overcoat that exposes a fourth metal pad formed at the second surface of the first die; and

a second wire bond coupled to the fourth metal pad.

15. The IC package of claim 14 , wherein the spacer plate and the second die have a footprint smaller than the first die.

16. The IC package of claim 13 , wherein the first die and the second die are galvanically isolated.

17. An integrated circuit (IC) package comprising:

a first die with a first surface overlaying a first substrate, wherein the first die comprises a first metal pad at a second surface opposing the first surface;

a second die comprising a second metal pad aligned with the first metal pad;

a first protective overcoat layer contacting the second surface of the first die, wherein the first protective overcoat layer comprises a first recess that exposes a third metal pad positioned at the second surface of the first die;

a second protective overcoat layer contacting a first surface of the second die;

a non-conductive die adhesive (NCDA) layer sandwiched between the first protective overcoat and the second protective overcoat, wherein the first metal pad and the second metal pad form a capacitor that couples the first die with the second die, wherein the NCDA layer overlays a portion of the first protective overcoat layer that is spaced apart from the first recess; and

a second substrate that contacts a second surface of the second die, wherein a second recess extending through the second substrate and an insulating layer of the second die exposes a portion of a metal layer to provide a fourth metal pad.

18. The IC package of claim 17 , further comprising:

a first wire bond coupled to the third metal pad; and

a second wire bond coupled to the fourth metal pad.

19. The IC package of claim 17 , wherein the first die and the second die are galvanically isolated.

20. The IC package of claim 17 , wherein the NCDA layer is a first NCDA layer, the IC package further comprising:

a second NCDA layer between the second protective overcoat and the first protective overcoat; and

a spacer between the first NCDA layer and the second NCDA layer.