Selector transistor with metal replacement gate wordline
A vertical transistor structure having a metal gate wordline. The vertical transistor structure can include an epitaxially grown semiconductor column surrounded by a thin gate dielectric layer. A gate structure can surround the semiconductor column and the gate dielectric layer. The device can include first and second dielectric layers and an electrically conductive metal layer located between the first and second dielectric layers. The electrically conductive metal of the gate structure can be tungsten (W). In addition, a thin layer of Ti or TiN can be formed between the metal gate layer and the first and second dielectric layers and the gate dielectric layer. The metal gate layer can be formed with or without the use of a sacrificial layer.
1. A method for manufacturing a memory array, the method comprising:
providing a semiconductor substrate;
depositing a first dielectric layer over the semiconductor substrate;
depositing a sacrificial layer over the first dielectric layer;
depositing a second dielectric layer over the sacrificial layer;
forming a plurality of vertical semiconductor columns in the sacrificial layer, the plurality of semiconductor columns extending to the substrate having a plurality of corresponding beveled recesses and each semiconductor column including a source and drain;
removing the sacrificial layer to form an open space adjacent to the semiconductor column;
depositing a protective and adhesion layer over the open space adjacent to the semiconductor column, the protective and adhesion layer coating the first dielectric layer and the second dielectric layer surrounding the open space; and
filling the open space with an electrically conductive metal.
2. The method as in claim 1 , wherein the sacrificial layer comprises silicon nitride.
3. The method as in claim 1 , wherein the electrically conductive metal comprises tungsten.
4. The method as in claim 1 , further comprising, before forming the semiconductor columns, forming an opening in the first and second dielectric layers and the sacrificial layer and then depositing a thin gate dielectric layer into the opening.
5. The method as in claim 1 , further comprising, after removing the sacrificial layer and before depositing the protective and adhesion layer, depositing a gate dielectric layer.
6. The method as in claim 5 , wherein the gate dielectric layer is one or more of silicon oxide and hafnium oxide.
7. The method as in claim 1 , wherein the sacrificial layer is removed by wet etch, and the method further comprises, after forming the semiconductor columns and before removing the sacrificial layer, performing a masking and etching process to remove a region of the second dielectric layer to facilitate removal of the sacrificial layer by wet etch.
8. The method as in claim 1 , wherein the sacrificial layer is removed by wet etch, and the method further comprises, after forming the semiconductor columns and before removing the sacrificial layer, performing a masking and etching process to remove a portion of the second dielectric layer and the sacrificial layer to facilitate removal of the sacrificial layer by wet etch.
9. The method as in claim 1 , further comprising forming a two terminal memory element, the two terminal memory element being electrically connected with the semiconductor column.
10. The method as in claim 1 , wherein the protective and adhesion layer comprises TiN.
11. A method for manufacturing a vertical transistor structure, the method comprising:
providing a substrate;
depositing a first dielectric layer on the substrate;
depositing a layer of metal on the first dielectric layer;
depositing a second dielectric layer on the layer of metal;
forming an opening in the second dielectric layer, layer of metal and first dielectric layer, the opening extending to the substrate, the opening having a beveled recess extending to the substrate; and
forming a semiconductor pillar and a surrounding gate dielectric layer into the opening, the semiconductor pillar being formed by selective epitaxial growth and having a source region and a drain region.
12. The method as in claim 11 , further comprising, after depositing the first dielectric layer and before depositing the layer of metal, depositing a layer of TiN.
13. The method as in claim 11 , wherein the layer of metal comprises tungsten.
14. A memory device comprising:
semiconductor column formed on a semiconductor substrate;
a gate dielectric layer surrounding the semiconductor column;
an electrically conductive metal gate line surrounding the gate dielectric layer and the semiconductor column; and
a two terminal resistive memory element electrically connected with the semiconductor column,
wherein the electrically conductive metal gate line is located between first and second dielectric layers, and the memory device further comprises a uniform TiN layer separating the electrically conductive metal gate line from the first and second dielectric layers and the gate dielectric layer.
15. The memory device as in claim 14 , wherein the electrically conductive metal gate line comprises tungsten.
16. The memory device as in claim 14 , wherein the semiconductor column comprises an epitaxially grown semiconductor.
17. The memory device as in claim 14 , wherein the semiconductor column comprises epitaxially grown semiconductor, the epitaxially grown semiconductor comprising one or more of silicon, silicon-germanium, gallium-arsenide, indium-gallium-arsenide or gallium indium zinc oxide.
18. The memory device as in claim 14 , further comprising a doped region in the semiconductor substrate, and wherein the semiconductor column is formed on the doped region in the semiconductor substrate.