Memory device and method for fabricating the same

1. A memory device, comprising:

a substrate;

an active layer that is spaced apart from the substrate and laterally oriented;

a word line that is laterally oriented in parallel to the active layer along one side of the active layer;

an active body that is vertically oriented by penetrating through the active layer;

a bit line that is vertically oriented by penetrating through the active layer to be spaced apart from one side of the active body; and

a capacitor that is vertically oriented by penetrating through the active layer to be spaced apart from another side of the active body.

2. The memory device of claim 1 , wherein the active layer and the word line are positioned at a same level from the substrate.

3. The memory device of claim 1 , wherein the active layer includes:

a first source/drain region coupled to the bit line;

a second source/drain region coupled to the capacitor; and

a channel body coupled to the active body and laterally oriented between the first source/drain region and the second source/drain region.

4. The memory device of claim 3 , wherein the channel body has a shape surrounding the active body.

5. The memory device of claim 1 , wherein the capacitor includes:

a storage node laterally oriented in parallel to the substrate;

a dielectric layer over the storage node; and

a plate node over the dielectric layer,

wherein the dielectric layer and the plate node are vertically oriented by penetrating through the storage node.

6. The memory device of claim 5 , wherein the storage node and the active layer are positioned at the same level.

7. The memory device of claim 1 , further comprising:

a bit line contact node formed in the active layer and surrounding the bit line.

8. The memory device of claim 1 , wherein at least one end of the word line has a stepped portion.

9. A memory device, comprising:

memory cells arranged vertically,

wherein each of the memory cells includes:

an active layer including a first source/drain region, a second source/drain region, and a channel body laterally oriented between the first source/drain region and the second source/drain region;

a word line laterally oriented in parallel to one side of the active layer;

an active body penetrating through the channel body;

a bit line vertically oriented by penetrating through the active layer to be coupled to the first source/drain region; and

a capacitor vertically oriented by penetrating through the active layer to be coupled to the second source/drain region.

10. The memory device of claim 9 , wherein the word line is parallel to the first source/drain area, the second source/drain area, and the channel body.

11. The memory device of claim 9 , further comprising:

a gate dielectric layer formed between one side of the channel body and the word line.

12. The memory device of claim 9 , further comprising:

an isolation dielectric layer between the first and second source/drain regions and the word line,

wherein the isolation dielectric layer is vertically oriented in a stacking direction of the memory cells.

13. The memory device of claim 9 , further comprising:

a bit line contact node that is formed in the active layer and coupled to the first source/drain region and the bit line,

wherein the bit line contact node surrounds the bit line.

14. The memory device of claim 9 , wherein at least one end of the word line has a stepped portion.

15. The memory device of claim 9 , wherein the capacitor includes:

a storage node formed in the active layer and coupled to the second source/drain region;

a dielectric layer over the storage node; and

a plate node over the dielectric layer.

16. The memory device of claim 15 , wherein the storage node and the active layer are positioned at the same level.

17. The memory device of claim 15 , wherein the dielectric layer and the plate node are vertically oriented to penetrate through the active layer.

18. The memory device of claim 9 , further comprising:

dielectric materials positioned between the memory cells.

19. The memory device of claim 9 , further comprising:

a peripheral circuit positioned below the memory cells.

20. The memory device of claim 9 , further comprising:

a peripheral circuit positioned above the memory cells.