Semiconductor device

1. A semiconductor device, comprising:

an insulating layer on a substrate;

channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other;

a gate electrode crossing the channel semiconductor patterns;

source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and

air gaps between the insulating layer and the bottom surfaces of the source/drain regions.

2. The device as claimed in claim 1 , wherein topmost portions of the air gaps are located at a level lower than a bottom surface of a bottommost one of the channel semiconductor patterns closest to the insulating layer.

3. The device as claimed in claim 1 , wherein bottommost portions of the air gaps are located at a level lower than a topmost surface of the insulating layer.

4. The device as claimed in claim 1 , wherein:

the source/drain regions are spaced apart from each other in a first direction,

each of the source/drain regions includes a pair of first semiconductor patterns, which are spaced apart from each other in the first direction, and

the first semiconductor patterns have lower portions and upper portions, widths of the lower portions in the first direction being larger than widths of the upper portions in the first direction.

5. The device as claimed in claim 1 , wherein:

the source/drain regions are spaced apart from each other in a first direction, and

each of the source/drain regions includes:

a pair of first semiconductor patterns, which are spaced apart from each other in the first direction, and

a second semiconductor pattern on the pair of first semiconductor patterns and connecting the pair of first semiconductor patterns.

6. The device as claimed in claim 5 , wherein:

the channel semiconductor patterns include a first semiconductor element,

each of the first semiconductor patterns and the second semiconductor pattern include a second semiconductor element, a lattice constant of the second semiconductor element being greater than a lattice constant of the first semiconductor element, and

a content of the second semiconductor element in the second semiconductor pattern is higher than a content of the second semiconductor element in each first semiconductor pattern.

7. The device as claimed in claim 5 , wherein topmost portions of the air gaps are defined by a bottom surface of each second semiconductor pattern.

8. The device as claimed in claim 1 , wherein:

the channel semiconductor patterns include a first semiconductor element,

the source/drain regions include the first semiconductor element and a second semiconductor element, a lattice constant of the second semiconductor element being greater than a lattice constant of the first semiconductor element, and

a content of the second semiconductor element in the source/drain regions decreases with decreasing distance from the insulating layer.

9. The device as claimed in claim 1 , wherein:

the source/drain regions are spaced apart from each other in a first direction,

each of the source/drain regions includes a pair of first semiconductor patterns spaced apart from each other in the first direction, and

bottommost portions of the first semiconductor patterns are located at a level lower than a topmost surface of the insulating layer.

10. The device as claimed in claim 1 , wherein:

the source/drain regions include:

a first semiconductor pattern covering side surfaces of the channel semiconductor patterns, and

a second semiconductor pattern on the first semiconductor pattern, and

the air gaps are defined by a bottom surface of the first semiconductor pattern, a bottom surface of the second semiconductor pattern, and a top surface of the insulating layer.

11. A semiconductor device, comprising:

an insulating layer on a substrate;

a first channel semiconductor pattern on the insulating layer and at a first vertical level;

a second channel semiconductor pattern stacked on the first channel semiconductor pattern and located at a second vertical level higher than the first vertical level;

a gate electrode crossing the first channel semiconductor pattern and the second channel semiconductor pattern; and

a source/drain region on a side surface of the gate electrode and connected to the first channel semiconductor pattern and the second channel semiconductor pattern,

wherein:

the source/drain region includes:

a first semiconductor pattern covering side surfaces of the first channel semiconductor pattern and the second channel semiconductor pattern, and

a second semiconductor pattern on the first semiconductor pattern, and

a width of the first semiconductor pattern at the first vertical level is larger than a width of the first semiconductor pattern at the second vertical level.

12. The device as claimed in claim 11 , wherein:

each of the first channel semiconductor pattern and the second channel semiconductor pattern includes a first semiconductor element and a second semiconductor element,

a lattice constant of the second semiconductor element is greater than a lattice constant of the first semiconductor element, and

a content of the second semiconductor element in the second semiconductor pattern is higher than a content of the second semiconductor element in the first semiconductor pattern.

13. The device as claimed in claim 11 , wherein a bottommost portion of the first semiconductor pattern is located at a level lower than a topmost surface of the insulating layer.

14. The device as claimed in claim 11 , further comprising an air gap between a bottom surface of the source/drain region and a top surface of the insulating layer.

15. The device as claimed in claim 14 , wherein a topmost portion of the air gap is located at a level lower than a bottom surface of the first channel semiconductor pattern.

16. A semiconductor device, comprising:

an insulating layer on a substrate;

a first channel stack on the insulating layer;

a second channel stack on the insulating layer and spaced apart from the first channel stack in a first direction, each of the first channel stack and the second channel stack including channel semiconductor patterns stacked to be vertically spaced apart from each other; and

a source/drain region between the first channel stack and the second channel stack,

wherein the source/drain region includes:

a pair of first semiconductor patterns covering side surfaces of the channel semiconductor patterns of the first channel stack and side surfaces of the channel semiconductor patterns of the second channel stack and being spaced apart from each other in the first direction, and

second semiconductor patterns on the pair of first semiconductor patterns and connecting the pair of first semiconductor patterns to each other.

17. The device as claimed in claim 16 , wherein the pair of first semiconductor patterns each include a protruding portion, the protruding portion of one first semiconductor pattern protruding toward the protruding portion of another first semiconductor pattern.

18. The device as claimed in claim 16 , further comprising an air gap between a bottom surface of the source/drain region and a top surface of the insulating layer.

19. The device as claimed in claim 18 , wherein a topmost portion of the air gap is located at a level lower than a bottom surface of a lowermost one of the channel semiconductor patterns of the first channel stack and the second channel stack.

20. The device as claimed in claim 18 , wherein a bottommost portion of the air gap is located at a level lower than a topmost surface of the insulating layer.