High-k gate dielectric

1. A semiconductor device, comprising:

a first transistor comprising:

a first active region,

a first gate dielectric layer over the first active region, the first gate dielectric layer comprising a first concentration of a dipole layer material, and

a first gate structure disposed over the first gate dielectric layer;

a second transistor comprising:

a second active region,

a second gate dielectric layer over the second active region, the second gate dielectric layer comprising a second concentration of the dipole layer material, and

a second gate structure disposed over the second gate dielectric layer; and

a third transistor comprising:

a third active region,

a third gate dielectric layer over the third active region, the third gate dielectric layer comprising a third concentration of the dipole layer material, and

a third gate structure disposed over the third gate dielectric layer,

wherein the dipole layer material comprises lanthanum oxide, aluminum oxide, or yittrium oxide,

wherein the first concentration is greater than the second concentration and the second concentration is greater than the third concentration,

wherein the first gate structure, the second gate structure and the third gate structure are substantially identical to one another structurally.

2. The semiconductor device of claim 1 , wherein the first gate structure, the second gate structure and the third gate structure are substantially identical to one another in terms of composition.

3. The semiconductor device of claim 1 , wherein the third concentration is zero.

4. The semiconductor device of claim 1 ,

wherein the first transistor, the second transistor and the third transistor are n-type transistors,

wherein the first transistor comprises a first threshold voltage, the second transistor comprises a second threshold voltage, and the third transistor comprises a third threshold voltage,

wherein the first threshold voltage is smaller than the second threshold voltage and the second threshold voltage is smaller than the third threshold voltage.

5. The semiconductor device of claim 1 ,

wherein the first transistor, the second transistor and the third transistor are p-type transistors,

wherein the first transistor comprises a first threshold voltage, the second transistor comprises a second threshold voltage, and the third transistor comprises a third threshold voltage,

wherein the first threshold voltage is greater than the second threshold voltage and the second threshold voltage is greater than the third threshold voltage.

6. The semiconductor device of claim 1 , wherein the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer further comprise hafnium oxide.

7. A method, comprising:

providing a workpiece comprising a first device region, a second device region and a third device region;

forming a first gate trench in the first device region, a second gate trench in the second device region, and a third gate trench in the third device region;

depositing a gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench;

depositing a first dipole layer over the gate dielectric layer in the first gate trench, the second gate trench, and the third gate trench;

selectively removing the first dipole layer in the second gate trench, wherein the selectively removing comprises:

depositing a hard mask layer over the workpiece,

depositing a bottom antireflective coating (BARC) layer over the hard mask layer,

patterning the BARC layer and the hard mask layer to expose the second gate trench, and

removing the first dipole layer in the second gate trench while the first gate trench and the third gate trench are covered by the hard mask layer and the BARC layer;

depositing a second dipole layer over the first dipole layer in the first gate trench, the gate dielectric layer in the second gate trench, and the first dipole layer in the third gate trench;

selectively removing the first dipole layer and the second dipole layer in the third gate trench; and

annealing the workpiece.

8. The method of claim 7 , further comprising:

after the annealing of the workpiece, removing the first dipole layer and the second dipole layer from the workpiece.

9. The method of claim 8 , furthering comprising:

after the removing of the first dipole layer and the second dipole layer from the workpiece, forming a common metal gate stack in the first gate trench, the second gate trench, and the third gate trench.

10. The method of claim 7 , wherein the first dipole layer and the second dipole layer comprise lanthanum oxide, aluminum oxide, or yittrium oxide.

11. The method of claim 7 , wherein the annealing of the workpiece comprises a temperature between about 500° C. and about 900° C.

12. The method of claim 7 , wherein the annealing of the workpiece comprises a duration between about 5 seconds and about 20 seconds.

13. The method of claim 7 , wherein a thickness of the first dipole layer and a thickness of the second dipole layer are between about 1 Å and about 10 Å.

14. The method of claim 7 ,

wherein the first dipole layer comprises a first thickness,

wherein the second dipole layer comprises a second thickness,

wherein the first thickness is substantially identically to the second thickness.

15. A method, comprising:

providing a workpiece comprising a first device region, a second device region, a third device region, and a fourth device region;

forming a first gate trench in the first device region, a second gate trench in the second device region, a third gate trench in the third device region, a fourth gate trench in the fourth device region;

depositing a gate dielectric layer in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench;

depositing a first dipole layer over the gate dielectric layer in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench;

selectively removing the first dipole layer in the third gate trench and the fourth gate trench;

performing a first anneal process to the workpiece;

removing the first dipole layer in the first gate trench and the second gate trench;

after the removing of the first dipole layer, depositing a second dipole layer over the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench;

selectively removing the second dipole layer in the second gate trench and the fourth gate trench;

performing a second anneal process to the workpiece;

removing the second dipole layer from the workpiece; and

after the removing of the second dipole layer, forming a common metal gate stack in the first gate trench, the second gate trench, the third gate trench, and the fourth gate trench.

16. The method of claim 15 ,

wherein the first dipole layer comprises a first thickness,

wherein the second dipole layer comprises a second thickness,

wherein the first thickness is greater than the second thickness.

17. The method of claim 16 , wherein the first thickness is between about 5 Å and about 10 Å and the second thickness is between about 1 Å and about 5 Å.

18. The method of claim 16 , wherein the first dipole layer and the second dipole layer comprise lanthanum oxide, aluminum oxide, or yittrium oxide.

19. The method of claim 16 , wherein the first anneal process and the second anneal process comprises a temperature between about 500° C. and about 900° C.

20. The method of claim 16 , wherein the first anneal process and the second anneal process comprises a duration between about 5 seconds and about 20 seconds.