Method of manufacturing a semiconductor device and a semiconductor device
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. At least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.
1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming a sacrificial gate structure over the fin structure;
etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
laterally etching the first semiconductor layers through the source/drain space;
forming an inner spacer made of a dielectric material on an end of each of the etched semiconductor layers; and
forming a source/drain epitaxial layer in the source/drain space to cover the inner spacer,
wherein at least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.
2. The method of claim 1 , wherein a lateral end of the at least one of the first semiconductor layers has a curved shape.
3. The method of claim 1 , wherein the first semiconductor layers are laterally etched by wet etching.
4. The method of claim 3 , wherein the wet etching comprises repeating wet etchings using a mixed solution of H 2 O 2 , CH 3 COOH and HF, followed by H 2 O cleaning.
5. The method of claim 1 , wherein the inner spacer is formed by:
forming a dielectric layer in the source/drain space; and
etching the dielectric layer, thereby leaving the inner spacer on the end of each of the etched first semiconductor layers remaining.
6. The method of claim 1 , further comprising, before the first semiconductors are laterally etched, forming sidewall spacers on side faces of the sacrificial gate structure,
wherein the sidewall spacers are made of a different material than the inner spacer.
7. The method of claim 6 , wherein the inner spacers include at least one of silicon nitride and silicon oxide.
8. The method of claim 6 , wherein the inner spacers include at least one of SiOC, SiOCN and SiCN.
9. The method of claim 1 , wherein in the etching a source/drain region of the fin structure, the first and second semiconductor layers of the source/drain region of the fin structure are etched.
10. The method of claim 1 , wherein in the etching a source/drain region of the fin structure, the first semiconductor layers of the source/drain region of the fin structure are selectively etched, thereby leaving the second semiconductor layers remaining.
11. The method of claim 1 , further comprising, after the source/drain epitaxial layer is formed:
removing the sacrificial gate structure, thereby exposing a part of the fin structure;
removing the first semiconductor layers from the exposed fin structure, thereby forming channel layers including the second semiconductor layers; and
forming a gate dielectric layer and a gate electrode layer around the channel layers,
wherein the gate electrode layer is isolated from the source/drain epitaxial layer by the inner spacer and the gate dielectric layer.
12. The method of claim 1 , wherein:
the first semiconductor layers are made of SiGe, and
the second semiconductor layers are made of Si.
13. The method of claim 12 , wherein in the at least one of the first semiconductor layers, a Ge concentration at a center region is smaller than a Ge concentration at edge regions along the stacked direction.
14. A method of manufacturing a semiconductor device, comprising:
forming a first fin structure and a second fin structure, wherein first semiconductor layers and second semiconductor layers are alternately stacked in each of the first fin structure and the second fin structure;
forming a first sacrificial gate structure over the first fin structure and a second sacrificial gate structure over the second fin structure;
while the second fin structure with the second sacrificial gate structure is protected,
etching a source/drain region of the first fin structure, which is not covered by the first sacrificial gate structure; thereby forming a first source/drain space;
laterally etching the first semiconductor layers in the first source/drain space;
forming a first inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers; and
forming a first source/drain epitaxial layer in the first source/drain space to cover the inner spacer, thereby forming a first structure;
while the first structure is protected,
etching the second semiconductor layers in a source/drain region of the second fin structure, which is not covered by the second sacrificial gate structure, thereby forming a second source/drain space;
laterally etching the second semiconductor layers through the second source/drain space;
forming a second inner spacer made of a dielectric material on an end of each of the etched second semiconductor layers; and
forming a second source/drain epitaxial layer in the second source/drain space to cover the second inner spacer, thereby forming a second structure,
wherein at least one of the first semiconductor layers has a composition which changes along a stacked direction of the first semiconductor layers and second semiconductor layers.
15. The method of claim 14 , wherein:
the first semiconductor layers are made of SiGe,
the second semiconductor layers are made of Si, and
in the at least one of the first semiconductor layers, a Ge concentration at a center region is smaller than a Ge concentration at edge regions along the stacked direction.
16. The method of claim 15 , wherein the Ge concentration at the center region is in a range from 15% to 35%, and the Ge concentration at the edge regions is in a range from 25% to 50%.
17. The method of claim 14 , wherein:
the first semiconductor layers are made of SiGe,
the second semiconductor layers are made of Si, and
in the at least one of the first semiconductor layers, a Ge concentration has two peaks and a reference Ge concentration region between the two peaks.
18. The method of claim 17 , wherein:
the Ge concentration Gp at the two peaks and the concentration Gr at the reference Ge concentration region satisfy 1.3×Gr≤Gp≤1.7×Gr.
19. A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming a sacrificial gate structure over the fin structure;
etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain space;
laterally etching the first semiconductor layers through the source/drain space;
forming an inner spacer made of a dielectric material on an end of each of the etched first semiconductor layers; and
forming a source/drain epitaxial layer in the source/drain space to cover the inner spacer, wherein:
the first semiconductor layers include Ge, and
in the at least one of the first semiconductor layers, a Ge concentration at a center region is smaller than a Ge concentration at edge regions along the stacked direction.
20. The method of claim 19 , wherein the Ge concentration at the center region is in a range from 15% to 35%, and the Ge concentration at the edge regions is in a range from 25% to 50%.