IP Library Granted Patent US 11,386,013
Granted Patent B2
US 11,386,013 · App. 16/902,909 · Granted Jul 12, 2022

Dynamic cache control mechanism

Inventors: Sudarshanram Shetty (Portland, OR); Ping Hang Cheung (Folsom, CA); Aravindh Anantaraman (Folsom, CA); Travis Schluessler (Berthoud, CO)
Assignee: Intel Corporation
G06F12/0893G06F9/30043G06F9/5016G06F11/3037G06F12/0862G06F12/0873G06F2212/1021
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Quick Facts
Patent No.
US 11,386,013
App. No.
16/902,909
Granted
Jul 12, 2022
Kind
B2
Abstract

An apparatus to facilitate dynamic cache control is disclosed. The apparatus includes one or more processors to profile execution characteristics of a graphics workload at a processing resource to generate profile data indicating a quantity of cache hits that occur at a cache memory and apply one or more cache settings to the cache memory based on the profile data.

Claims (22)

1. An apparatus to facilitate dynamic cache control, comprising:

one or more processors to profile execution characteristics of a graphics workload at each of a plurality of processing resources to generate profile data indicating a quantity of cache hits that occur at a cache memory, including monitoring cache hits to each of a plurality of cache chunks and recording the cache hits in a plurality of sector maps, retrieve the profile data from the sector map indicating frequently used cache lines and apply one or more cache settings to the cache memory based on the retrieved frequently used cache lines indicated in the profile data, wherein each of the plurality of sector maps is associated with an identified critical resource, wherein a critical resource comprises a resource continuously accessed during a processing time of an image frame or consumed for a significant time period during the processing time of the image frame.

2. The apparatus of claim 1 , wherein the one or more processors further monitor cache hits to each of a plurality of cache chunks and record the cache hits in a sector of the sector map associated with each of the plurality of cache chunks.

3. The apparatus of claim 2 , wherein the one or more processors monitoring the execution characteristics further comprises decoding cache memory requests.

4. The apparatus of claim 3 , wherein the one or more processors decode cache memory request into a surface identifier and address offsets included in the cache memory requests.

5. The apparatus of claim 4 , wherein the one or more processors maps the address offsets to an entry in the sector map.

6. The apparatus of claim 1 , wherein the one or more processors apply a setting to prefetch the frequently used cache lines indicated in the sector map.

7. The apparatus of claim 5 , wherein the one or more processors profiling the execution characteristics comprises monitoring the workload execution characteristics to identify resources consumed during execution of the graphics workload.

8. The apparatus of claim 7 , wherein the one or more processors identify one or more resources that are critical resources.

9. The apparatus of claim 8 , wherein the one or more processors generate a sector map for each of the critical resources.

10. A method to facilitate dynamic cache control, comprising:

profiling execution characteristics of a graphics workload at each of a plurality of processing resources to generate profile data indicating a quantity of cache hits that occur at a cache memory, including:

monitoring cache hits to a cache memory during execution of the graphics workload; and

recording the cache hits to the cache memory in a plurality of sector maps as profile data, wherein each of the plurality of sector maps is associated with an identified critical resource, wherein a critical resource comprises a resource continuously accessed during a processing time of an image frame or consumed for a significant time period during the processing time of the image frame; retrieving the profile data from the sector map indicating frequently used cache lines; and applying one or more cache settings to the cache memory based on the profile data.

11. The method of claim 10 , wherein monitoring cache hits comprises: decoding cache memory requests into a surface identifier and address offsets included in the cache memory requests; and mapping the address offsets to an entry in the sector map.

12. The method of claim 10 , further comprising applying a setting to prefetch frequently used cache lines indicated in the sector map.

13. At least one non-transitory computer readable medium having instructions stored thereon, which when executed by one or more processors, cause the processors to:

profile execution characteristics of a graphics workload at each of a plurality of processing resources to generate profile data indicating a quantity of cache hits that occur at a cache memory, including:

monitoring cache hits to a cache memory during execution of the graphics workload; and recording the cache hits to the cache memory in a plurality of sector maps as profile data, wherein each of the plurality of sector maps is associated with an identified critical resource, wherein a critical resource comprises a resource continuously accessed during a processing time of an image frame or consumed for a significant time period during the processing time of the image frame;

retrieving the profile data from the sector map indicating frequently used cache lines; and apply one or more cache settings to the cache memory based on the profile data.

14. The computer readable medium of claim 13 , wherein monitoring cache hits comprises: decoding cache memory requests into a surface identifier and address offsets included in the cache memory requests; and mapping the address offsets to an entry in the sector map.

15. The computer readable medium of claim 13 , having instructions stored thereon, which when executed by one or more processors, further cause the processors to apply a setting to prefetch frequently used cache lines indicated in the sector map.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2020
From: SHETTY, SUDARSHANRAM; CHEUNG, PING HANG; ANANTARAMAN, ARAVINDH; SCHLUESSLER, TRAVIS
To: INTEL CORPORATION
Reel/Frame 053088/0442 →
Continuity (1)
Related Publication 20210390058A1 · Dec 16, 2021
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