Stackable fully molded semiconductor structure with vertical interconnects

1. A method of making a semiconductor device, comprising:

providing a carrier;

forming a planar conductive seed layer over the carrier;

forming a first photoresist over the carrier and the planar conductive seed layer;

patterning the first photoresist layer to form first openings through the first photoresist that extend to the planar conductive seed layer;

forming a non-planar conductive seed layer over the first photoresist that conformally extends into the first openings through the first photoresist;

forming a second photoresist over the first photoresist, within the first openings, and over the non-planar conductive seed layer;

patterning the second photoresist layer to form second openings through the second photoresist that align with the first openings and extend to the non-planar conductive seed layer;

plating copper posts over the non-planar conductive seed layer and within the first openings and the second openings;

stripping the second photoresist while leaving in place the first photoresist;

coupling a semiconductor die to the carrier in a face up orientation, with a die attach film coupled to the carrier and disposed between the backside of the semiconductor die and the carrier;

encapsulating the semiconductor die and a portion of the copper posts exposed from the first photoresist with a mold compound;

forming a conductive redistribution layer (RDL) over the mold compound and coupled with first ends of the copper posts and the active surface of the semiconductor die;

removing the carrier and the second photoresist after encapsulating the semiconductor with the mold compound to expose second ends and adjacent sides of the copper posts; and

forming conductive bumps over exposed second ends and adjacent sides of the copper posts.

2. The method of claim 1 , further comprising:

providing the carrier as a reusable carrier;

forming a release layer over the reusable carrier; and

removing the carrier by activating the release layer.

3. The method of claim 2 , further comprising:

forming the planar conductive seed layer of TiCu and over the release layer; and

using the TiCu planar conductive seed layer as a protective barrier for the release layer before removing the carrier by activating the release layer.

4. The method of claim 1 , wherein the copper posts comprise a step along a sidewall of the copper posts formed where the first photoresist layer meets the second photoresist layer within the second opening.

5. The method of claim 1 , further comprising removing the carrier and the second photoresist after encapsulating the semiconductor with the mold compound to form a recessed portion of a bottom surface of the mold compound.

6. The method of claim 5 , further comprising forming a rim of mold compound with a width of 10-100 μm around a periphery of the semiconductor die and adjacent to the recessed portion of the bottom surface of the mold compound.

7. The method of claim 1 , further comprising forming a package on package (POP) structure by coupling a first semiconductor device of claim 1 over a second semiconductor device of claim 1 .

8. A method of making a semiconductor device, comprising:

providing a carrier;

forming a first photoresist over the carrier with first openings through the first photoresist;

forming a non-planar conductive seed layer over the first photoresist that conformally extends into the first openings through the first photoresist;

forming a second photoresist over the first photoresist and over the non-planar conductive seed layer;

patterning the second photoresist layer to form second openings through the second photoresist and extend to the non-planar conductive seed layer;

plating conductive posts over the non-planar conductive seed layer and within the second openings;

removing the second photoresist while leaving in place the first photoresist;

coupling a semiconductor die to the carrier; and

encapsulating the semiconductor die, the conductive posts, and the first photoresist with a mold compound.

9. The method of claim 8 , further comprising plating conductive posts over the non-planar conductive seed layer and within the second openings.

10. The method of claim 9 , further comprising:

removing the carrier and the second photoresist after encapsulating the semiconductor with the mold compound to form a recessed portion of a bottom surface of the mold compound; and

forming a rim of mold compound around a periphery of the semiconductor die and adjacent the recessed portion of the bottom surface of the mold compound.

11. The method of claim 8 , further comprising plating the conductive posts over the non-planar conductive seed layer and outside of, and offset from, the second openings.

12. The method of claim 8 , further comprising forming conductive bumps over exposed ends and adjacent sides of the conductive posts.

13. The method of claim 9 , wherein the conductive posts comprise a step along a sidewall of the conductive posts formed where the first photoresist layer meets the second photoresist layer within the second opening.

14. A method of making a semiconductor device, comprising:

providing a carrier comprising a semiconductor die mounting site;

forming a first photoresist layer over the carrier;

forming a seed layer over the first photoresist;

forming a second photoresist over the first photoresist and with second openings in the second photoresist over the seed layer;

forming conductive posts within the second openings and in a periphery of the semiconductor die mounting site;

stripping the second photoresist while leaving in place the first photoresist before encapsulating a semiconductor die;

disposing the semiconductor die at the semiconductor die mounting site;

encapsulating the semiconductor die and the conductive posts with an encapsulant; and

removing the first photoresist layer such that at least one end of the conductive posts are made to be offset with respect to the encapsulant.

15. The method of claim 14 , further comprising:

forming first openings through the first photoresist; and

forming the second openings within the first openings and extending to the seed layer.

16. The method of claim 15 , wherein:

forming the first openings through the first photoresist occurs before forming the seed layer; and

the seed layer conformally extends into the first openings in the first photoresist layer.

17. The method of claim 14 , further comprising forming conductive bumps over exposed ends and adjacent sides of the conductive posts.

18. The method of claim 14 , further comprising:

forming a recessed portion of a bottom surface of the encapsulant; and

forming a rim of encapsulant around a periphery of the semiconductor die and adjacent the recessed portion of the bottom surface of encapsulant.

19. The method of claim 15 , further comprising plating the conductive posts over the seed layer outside of the first openings, and offset from the first openings.