Semiconductor device

1. A semiconductor device comprising:

first and second memory cells arranged on a semiconductor substrate,

wherein the first memory cell includes, between a first source region and a first drain, a configuration in which a first selection gate and a first floating gate are arranged in series adjacent to each other in a direction parallel to a surface of the semiconductor substrate and without overlapping each other in a direction perpendicular to the surface,

the second memory cell includes, between a second source region and a second drain, a configuration in which a second selection gate and a second floating gate are arranged in series adjacent to each other in the direction parallel to the surface of the semiconductor substrate and without overlapping each other in a direction perpendicular to the surface,

the first memory cell and the second memory cell are adjacent to each other in a first direction,

a first signal line extending in the first direction and connected to the first selection gate and the second selection gate is further provided,

the first source region and the second source region are configured to share a first region, and

the first selection gate extends in a direction different from the first direction.

2. The semiconductor device according to claim 1 , wherein:

the first memory cell further includes a first deletion region that does not include the first source region and the first drain region, and

the first floating gate extends to the first deletion region.

3. The semiconductor device according to claim 1 , wherein

the first selection gate and the second selection gate are arranged in such orientation that the first selection gate and the second selection gate are symmetric with respect to an axis of symmetry, the axis of symmetry being a boundary between the first memory cell and the second memory cell.

4. The semiconductor device according to claim 1 , wherein

another memory cell adjacent to the first memory cell in a direction different from the first direction is further provided,

the another memory cell has, between another source region and another drain, a configuration in which another selection gate and another floating gate are arranged in series, and

the first source region and the another source region are formed to share the first region.

5. The semiconductor device according to claim 1 , further comprising:

third and fourth memory cells arranged on the semiconductor substrate,

wherein the third memory cell includes, between a third source region and a third drain, a configuration in which a third selection gate and a third floating gate are arranged in series,

the fourth memory cell includes, between a fourth source region and a fourth drain, a configuration in which a fourth selection gate and a fourth floating gate are arranged in series,

the third memory cell and the fourth memory cell are adjacent to each other in the first direction,

a second signal line extending in the first direction and connected to the third selection gate and the fourth selection gate is further provided,

the third source region and the fourth source region are configured to share a second region,

the first region and the second region are different regions, and

the first memory cell and the third memory cell are adjacent to each other in the second direction different from the first direction.

6. The semiconductor device according to claim 5 , further comprising:

a third signal line extending in the first direction and connected to the first region and the second region.

7. The semiconductor device according to claim 5 , wherein

the first selection gate and the third selection gate are electrically connected to each other.

8. The semiconductor device according to claim 1 , wherein a diffusion connection region is provided each of between the first selection gate and the first floating gate and between the second selection gate and the second floating gate.