Control method and controller of program suspending and resuming for memory
A control method, for a memory array, the control method comprises programming the bit-cell of the memory array in a programming stage; and discharging the bit-cell of the memory array in a discharge stage; wherein the programming stage comprises: programming the bit-cell of the memory array with a plurality of programming voltage pulses; wherein the discharge stage comprises: isolating a select line of the bit-cell of the memory array; and generating a programming voltage pulse to the bit-cell of the memory array; wherein the programming stage can be suspended to a suspend stage by a suspend command after the discharge stage; wherein the suspend command is received during one of the plurality of programming voltage pulse.
1. A control method, for a memory array, comprising:
programming the bit-cell of the memory array in a programming stage; and
discharging the bit-cell of the memory array in a discharge stage;
wherein the programming stage comprises:
programming the bit-cell of the memory array with a plurality of programming voltage pulses;
wherein the discharge stage comprises:
isolating a select line of the bit-cell of the memory array; and
generating a programming voltage pulse to the bit-cell of the memory array;
wherein the programming stage is suspended to a suspend stage by a suspend command after the discharge stage;
wherein the suspend command is received during one of the plurality of programming voltage pulse.
2. The control method of claim 1 , further comprising:
verification the bit-cell of the memory array in a verification stage;
wherein the verification stage comprises:
verifying whether the bit-cell of the memory array is programmed;
wherein when there is no suspend command, the verification stage follows the programming stage;
wherein when there is a suspend command, the verification stage follows the discharge stage.
3. The control method of claim 1 , further comprising:
enabling a bottom select gate line of an interface to discharge the bit-cell of the memory in the discharge stage.
4. The control method of claim 1 , wherein the discharge stage is overlapped with the programming stage in time.
5. The control method of claim 1 , further comprising:
generating a clean voltage pulse to discharge the bit-cell of the memory array in the discharge stage.
6. The control method of claim 1 , further comprising:
generating a dummy programming voltage pulse in the discharge stage.
7. The control method of claim 6 , further comprising:
executing the dummy programming voltage pulse by a dummy programming command.
8. The control method of claim 1 , wherein the discharge stage follows each of the plurality of programming voltage pulses.
9. The control method of claim 1 , further comprising:
keeping voltages and waveforms of a top select gate line and a bottom select gate line of an interface to be the same as those in the programming stage in the discharge stage.
10. A controller for programming a memory array, comprising:
a storage unit, configured to store a program code; and
a processing unit, configured to perform the following steps:
programming the bit-cell of the memory array in a programming stage; and
discharging the bit-cell of the memory array in a discharge stage;
wherein the programming stage comprises:
programming the bit-cell of the memory array with a plurality of programming voltage pulses;
wherein the discharge stage comprises:
isolating a select line of the bit-cell of the memory array; and
generating a programming voltage pulse to the bit-cell of the memory array;
wherein the programming stage is suspended to a suspend stage by a suspend command after the discharge stage.
11. The controller for programming a memory array of claim 10 , the programming stage further comprising:
verification the bit-cell of the memory array in a verification stage;
wherein the verification stage comprises:
verifying whether the bit-cell of the memory array is programmed;
wherein when there is no suspend command, the verification stage follows the programming stage;
wherein when there is a suspend command, the verification stage follows the discharge stage;
wherein the suspend command is received during one of the plurality of programming voltage pulse.
12. The controller for programming a memory array of claim 10 , wherein the controller further enables a bottom select gate line of an interface to discharge the bit-cell of the memory in the discharge stage.
13. The controller for programming a memory array of claim 10 , wherein the discharge stage is overlapped with the programming stage in time.
14. The controller for programming a memory array of claim 10 , wherein the controller further generates a clean voltage pulse to discharge the bit-cell of the memory array in the discharge stage.
15. The controller for programming a memory array of claim 10 , wherein the controller further generates a dummy programming voltage pulse in the discharge stage.
16. The controller for programming a memory array of claim 15 , wherein the controller further executes the dummy programming voltage pulse by a dummy programming command.
17. The controller for programming a memory array of claim 10 , wherein the discharge stage follows each of the plurality of programming voltage pulses.
18. The controller for programming a memory array of claim 10 , wherein the controller further keeps voltages and waveforms of a top select gate line and a bottom select gate line of an interface to be the same as those in the programming stage in the discharge stage by the controller.