Maintaining safe operating area operation of transistors during ramp up
Systems and methods are described for controlling inrush current for a system comprising a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs). The system may include a control circuit coupled to parallel series of gate drivers, where each gate driver is coupled to a different MOSFET. An inrush current may be received during charging of a capacitor of the switch circuit. During a first period of a ramp time, the control circuit may cause the inrush current to pass through a first gate driver. During a second period of the ramp time, the control circuit may cause the inrush current to pass through a second gate driver. By using a control circuit to cause the inrush current to pass through each MOSFET, a gate-source threshold voltage for the MOSFETs may remain below safe operating areas (SOAs) for the different MOSFETs.
1. A method for controlling inrush current for a system comprising a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs), the method comprising:
receiving an inrush current during charging of a capacitor of the system, the system comprising a control circuit communicatively coupled to a plurality of gate drivers, where each gate driver is communicatively coupled to a gate of a different MOSFET of the plurality of MOSFETs coupled in parallel;
during a first period of a ramp time, causing, using the control circuit via a first gate driver, a greater portion of the inrush current to pass through a first MOSFET of the plurality of MOSFETs relative to a second MOSFET of the plurality of MOSFETs; and
during a second period of the ramp time, causing, using the control circuit via a second gate driver, a greater portion of the inrush current to pass through the second MOSFET of the plurality of MOSFETs relative to the first MOSFET, the second gate driver having a greater slew rate than the first gate driver.
2. The method of claim 1 , where the plurality of MOSFETs comprises two MOSFETs.
3. The method of claim 1 , where the plurality of MOSFETs comprises more than two MOSFETs.
4. The method of claim 1 , wherein each MOSFET of the plurality of MOSFETs has the same specifications.
5. The method of claim 1 , where each gate driver is assigned to a different pin of the switch circuit.
6. A switch circuit that controls inrush current comprising:
a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) coupled in parallel, each MOSFET comprising a source, a drain, and a gate;
a plurality of gate drivers, where each gate driver is communicatively coupled to a gate of a different MOSFET of the plurality of MOSFETs;
a capacitor coupled to the plurality of MOSFETs; and
a control circuit communicatively coupled to each of the plurality of gate drivers, wherein when an inrush current is received by the switch circuit during a ramp time to charge the capacitor, the control circuit causes a greater portion of the inrush current to pass through a first MOSFET of the plurality of MOSFETs via a first gate driver of the plurality of gate drivers during a first period of the ramp time relative to a second MOSFET of the plurality of MOSFETs, and the control circuit causes a greater portion of the inrush current to pass through the second MOSFET of the plurality of MOSFETs via a second gate driver of the plurality of gate drivers during a second period of the ramp time relative to the first MOSFET, the second gate driver having a greater slew rate than the first gate driver.
7. The switch circuit of claim 6 , where the plurality of MOSFETs comprises two MOSFETs.
8. The switch circuit of claim 6 , where the plurality of MOSFETs comprises more than two MOSFETs.
9. The switch circuit of claim 6 , wherein each MOSFET of the plurality of MOSFETs has the same specifications.
10. The switch circuit of claim 6 , where each gate driver is assigned to a different pin of the switch circuit.