Display device and method of fabricating the same

1. A display device comprising:

a substrate;

a first active layer of a first transistor and a second active layer of a second transistor on the substrate;

a first gate insulating layer on the first active layer;

a first gate electrode on the first gate insulating layer;

a second gate insulating layer on the second active layer; and

a second gate electrode on the second gate insulating layer,

wherein a hydrogen concentration of each layer of material between the first gate electrode and the first active layer, including the first gate insulating layer, is lower than a hydrogen concentration of the second gate insulating layer.

2. The display device of claim 1 , wherein a minimum thickness of the first gate insulating layer is greater than a minimum thickness of the second gate insulating layer.

3. The display device of claim 1 , wherein the second gate insulating layer is on the first gate electrode.

4. The display device of claim 3 , wherein the second gate insulating layer is on an upper surface and side surfaces of the first gate electrode.

5. The display device of claim 3 , wherein the second gate insulating layer is on side surfaces of the first gate insulating layer.

6. The display device of claim 3 , further comprising:

a capacitor electrode on the second gate insulating layer and overlapping with the first gate electrode in a first direction that is a thickness direction of the substrate.

7. The display device of claim 6 , wherein the capacitor electrode is on an upper surface of the second gate insulating layer, and is in a portion of each of side surfaces of the second gate insulating layer.

8. The display device of claim 7 , wherein the capacitor electrode overlaps with the first gate electrode in a second direction intersecting the first direction.

9. The display device of claim 6 , wherein the first active layer comprises a first channel region, a first source region on a first side of the first channel region, and a first drain region on a second side of the first channel region.

10. The display of claim 9 , wherein the first gate insulating layer is on the first channel region, and the second gate insulating layer is on a portion of the first source region and a portion of the first drain region.

11. The display device of claim 9 , further comprising:

an interlayer dielectric layer on the capacitor electrode;

a first source electrode on the interlayer dielectric layer and connected to another portion of the first source region through a first contact hole penetrating through the interlayer dielectric layer; and

a first drain electrode on the interlayer dielectric layer and connected to another portion of the first drain region through a second contact hole penetrating through the interlayer dielectric layer.

12. The display device of claim 11 , further comprising:

a light shielding layer on the substrate and overlapping with the first channel region in the first direction; and

a buffer layer between the light shielding layer and the first active layer,

wherein the first source electrode is connected to the light shielding layer through a contact hole penetrating through the interlayer dielectric layer and the buffer layer.

13. The display device of claim 11 , further comprising:

a supply voltage line on the interlayer dielectric layer and connected to the capacitor electrode through a third contact hole penetrating through the interlayer dielectric layer.

14. The display device of claim 9 , wherein the second active layer comprises a second channel region, a second source region on one side of the second channel region, and a second drain region on an opposite side of the second channel region.

15. The display device of claim 14 , wherein the second gate insulating layer is on the second channel region.

16. The display device of claim 14 , further comprising:

an interlayer dielectric layer on the second gate electrode;

a second source electrode on the interlayer dielectric layer and connected to another portion of the second source region through a fourth contact hole penetrating through the interlayer dielectric layer; and

a second drain electrode on the interlayer dielectric layer and connected to another portion of the second drain region through a fifth contact hole penetrating through the interlayer dielectric layer.

17. The display device of claim 1 , wherein the first gate insulating layer and the second gate insulating layer comprise a silicon oxide layer.

18. The display device of claim 1 , wherein the first active layer and the second active layer are formed of an oxide semiconductor comprising indium, gallium, and oxygen.

19. A method of fabricating a display device, the method comprising:

forming a first active layer of a first transistor and a second active layer of a second transistor on a substrate;

forming a first gate insulating layer on a first channel region of the first active layer, and a first gate electrode of the first transistor on the first gate insulating layer, the first gate electrode overlapping the first channel region in a first direction that is a thickness direction of the substrate; and

forming a second gate insulating layer on a second channel region of the second active layer, and a second gate electrode of the second transistor on the second gate insulating layer, the second gate electrode overlapping the second channel region in the first direction,

wherein a hydrogen concentration of each layer of material between the first gate electrode and the first active layer, including the first gate insulating layer is lower than a hydrogen concentration of the second gate insulating layer.

20. The method of claim 19 , wherein a minimum thickness of the first gate insulating layer is greater than a minimum thickness of the second gate insulating layer.

21. The method of claim 19 , wherein the forming the second gate electrode of the second transistor on the second gate insulating layer comprises:

forming a capacitor electrode on the second gate insulating layer such that it overlaps with the first gate electrode in the first direction.

22. The method of claim 21 , wherein the capacitor electrode overlaps with the first gate electrode in a second direction intersecting the first direction.