Partial refresh technique to save memory refresh power
In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.
1. A system-on-chip (SOC), comprising:
a memory controller; and
a PHY block configured to communicate with a memory device comprising a plurality of memory cells and a partial array refresh (PAR) mask register,
wherein the memory controller is configured to issue, via the PHY block, self-refresh-enter (SRE) and self-refresh-exit (SRX) commands to instruct the memory device to enter into and exit from a self-refresh (SR) mode, respectively, and
wherein when the memory device is in the SR mode and a partial array self-refresh (PASR) is enabled, the memory device is configured to internally refresh a subset of the plurality of memory cells selected in accordance with the PAR mask register without receiving a refresh (REF) command from the SOC.
2. The SOC of claim 1 , wherein the memory controller is configured to issue, via the PHY block, an enable PASR command to instruct the memory device to enable the PASR.
3. The SOC of claim 2 ,
wherein the memory device further comprises one or more mode registers (MR) to implement a PAR enable register comprising a PASR enable bit, the PASR enable bit when set/unset indicating that the PASR is enabled/disabled, and
wherein the enable PASR command is a mode register write (MRW) command to instruct the memory device to set the PASR enable bit of the PAR enable register.
4. The SOC of claim 1 , wherein the memory controller is configured to issue, via the PHY block, a set PAR mask command to instruct the memory device to set the PAR mask register.
5. The SOC of claim 4 ,
wherein the memory device further comprises one or more mode registers (MR) to implement the PAR mask register, and
wherein the set PAR mask command is a mode register write (MRW) command with a corresponding mask value to instruct the memory device to write the mask value into the PAR mask register, the mask value indicating a refresh skip region comprising one or more portions of the plurality of memory cells that do not require refreshing.
6. The SOC of claim 5 , wherein the memory controller is configured to:
receive the refresh skip region from a memory driver of a computing system, and
issue the set PAR mask command with the corresponding mask value subsequent to receiving the refresh skip region from the memory driver.
7. The SOC of claim 5 ,
wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments,
wherein the PAR mask register comprises a plurality of segment mask bits, each segment mask bit corresponding to a segment and indicating whether a refresh is enabled or disabled for the corresponding segment, and
wherein for each segment of each bank, that segment of that bank is included in the skip region when the corresponding segment mask bit indicates that the refresh is disabled for that segment.
8. The SOC of claim 5 ,
wherein the plurality of memory cells is partitioned into a plurality of banks,
wherein the PAR mask register comprises a plurality of bank mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and
wherein for each bank, that bank is included in the skip region when the corresponding bank mask bit indicates that the refresh is disabled for that bank.
9. The SOC of claim 5 ,
wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments,
wherein the PAR mask register includes a plurality of bank mask bits and a plurality of segment mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and each segment mask bit corresponding to a segment and indicating whether a refresh is enabled or disabled for the corresponding segment, and
wherein for each segment of each bank, that segment of that bank is included in the skip region when either
the corresponding segment mask bit indicates that the refresh is disabled for that segment, or
the corresponding bank mask bit indicates that the refresh is disabled for that bank.
10. The SOC of claim 5 ,
wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments,
wherein the PAR mask register includes a plurality of bank mask bits and a plurality of segment mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and each segment mask bit corresponding to a segment and indicating whether a refresh is enabled or disabled for the corresponding segment, and
wherein for each segment of each bank, that segment of that bank is included in the skip region when both
the corresponding segment mask bit indicates that the refresh is disabled for that segment, and
when the corresponding bank mask bit indicates that the refresh is disabled for that bank.
11. The SOC of claim 1 , wherein the SOC is incorporated in an apparatus comprising a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in an automotive vehicle.
12. A method of a system-on-chip (SOC) configured to communicate with a memory device comprising a plurality of memory cells and a partial array refresh (PAR) mask register, the method comprising:
issuing an enable partial array self-refresh (PASR) command to the memory device to enable a PASR; and
issuing a self-refresh-enter (SRE) commands to instruct the memory device to enter into a self-refresh (SR) mode,
wherein when the memory device is in the SR mode and the PASR is enabled, the memory device is configured to internally refresh a subset of the plurality of memory cells selected in accordance with the PAR mask register without receiving a refresh (REF) command from the SOC.
13. The method of claim 12 ,
wherein the memory device further comprises one or more mode registers (MR) to implement a PAR enable register comprising a PASR enable bit, the PASR enable bit when set/unset indicating that the PASR is enabled/disabled, and
wherein issuing the enable PASR comprises issuing a mode register write (MRW) command to instruct the memory device to set the PASR enable bit of the PAR enable register.
14. The method of claim 12 , further comprising:
issuing a set PAR mask command to instruct the memory device to set the PAR mask register.
15. The method of claim 14 ,
wherein the memory device further comprises one or more mode registers (MR) to implement the PAR mask register, and
wherein issuing the set PAR mask command comprises issuing a mode register write (MRW) command with a corresponding mask value to instruct the memory device to write the mask value into the PAR mask register, the mask value indicating a refresh skip region comprising one or more portions of the plurality of memory cells that do not require refreshing.
16. The method of claim 15 , further comprising:
receiving the refresh skip region from a memory driver of a computing system,
wherein the set PAR mask command with the corresponding mask value is issued subsequent to receiving the refresh skip region from the memory driver.
17. The method of claim 15 ,
wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments,
wherein the PAR mask register comprises a plurality of segment mask bits, each segment mask bit corresponding to a segment and indicating whether a refresh is enabled or disabled for the corresponding segment, and
wherein for each segment of each bank, that segment of that bank is included in the skip region when the corresponding segment mask bit indicates that the refresh is disabled for that segment.
18. The method of claim 15 ,
wherein the plurality of memory cells is partitioned into a plurality of banks,
wherein the PAR mask register comprises a plurality of bank mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and
wherein for each bank, that bank is included in the skip region when the corresponding bank mask bit indicates that the refresh is disabled for that bank.
19. The method of claim 15 ,
wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments,
wherein the PAR mask register includes a plurality of bank mask bits and a plurality of segment mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and each segment mask bit corresponding to a segment and indicating whether a refresh is enabled or disabled for the corresponding segment, and
wherein for each segment of each bank, that segment of that bank is included in the skip region when either
the corresponding segment mask bit indicates that the refresh is disabled for that segment, or
the corresponding bank mask bit indicates that the refresh is disabled for that bank.
20. The method of claim 15 ,
wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments,
wherein the PAR mask register includes a plurality of bank mask bits and a plurality of segment mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and each segment mask bit corresponding to a segment and indicating whether a refresh is enabled or disabled for the corresponding segment, and
wherein for each segment of each bank, that segment of that bank is included in the skip region when both
the corresponding segment mask bit indicates that the refresh is disabled for that segment, and
when the corresponding bank mask bit indicates that the refresh is disabled for that bank.
21. An apparatus, comprising:
a system-on-chip (SOC); and
a memory device,
wherein the SOC and the memory device are configured to communicate with each other over a link,
wherein the memory device comprises:
a plurality of memory cells; and
a partial array refresh (PAR) mask register,
wherein the SOC is configured to issue self-refresh-enter (SRE) and self-refresh-exit (SRX) commands over the link to instruct the memory device to enter into and exit from a self-refresh (SR) mode, respectively, and
wherein when the memory device is in the SR mode and a partial array self-refresh (PASR) is enabled, the memory device is configured to internally refresh a subset of the plurality of memory cells selected in accordance with the PAR mask register without receiving a refresh (REF) command from the SOC.
22. The apparatus of claim 21 , wherein the SOC is configured to issue, over the link, an enable PASR command to instruct the memory device to enable the PASR.
23. The apparatus of claim 22 ,
wherein the memory device further comprises one or more mode registers (MR) to implement a PAR enable register comprising a PASR enable bit, the PASR enable bit when set/unset indicating that the PASR is enabled/disabled, and
wherein the enable PASR command is a mode register write (MRW) command to instruct the memory device to set the PASR enable bit of the PAR enable register.
24. The apparatus of claim 21 , wherein the SOC is configured to issue, over the link, a set PAR mask command to instruct the memory device to set the PAR mask register.
25. The apparatus of claim 24 ,
wherein the memory device further comprises one or more mode registers (MR) to implement the PAR mask register, and
wherein the set PAR mask command is a mode register write (MRW) command with a corresponding mask value to instruct the memory device to write the mask value into the PAR mask register, the mask value indicating a refresh skip region comprising one or more portions of the plurality of memory cells that do not require refreshing.
26. The apparatus of claim 25 , wherein the SOC is configured to:
receive the refresh skip region from a memory driver of a computing system, and
issue the set PAR mask command with the corresponding mask value subsequent to receiving the refresh skip region from the memory driver.
27. The apparatus of claim 25 ,
wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments,
wherein the PAR mask register comprises a plurality of segment mask bits, each segment mask bit corresponding to a segment and indicating whether a refresh is enabled or disabled for the corresponding segment, and
wherein when the memory device is in the SR mode and the PASR is enabled, the memory device is configured to, for each bank, skip the internal refreshing of each segment of that bank whose corresponding segment mask bit indicates that the refresh is disabled for that segment.
28. The apparatus of claim 25 ,
wherein the plurality of memory cells is partitioned into a plurality of banks,
wherein the PAR mask register comprises a plurality of bank mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and
wherein when the memory device is in the SR mode and the PASR is enabled, the memory device is configured to skip the internal refreshing of each bank whose corresponding segment mask bit indicates that the refresh is disabled for that bank.
29. The apparatus of claim 25 ,
wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments,
wherein the PAR mask register includes a plurality of bank mask bits and a plurality of segment mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and each segment mask bit corresponding to a segment and indicating whether a refresh is enabled or disabled for the corresponding segment, and
wherein when the memory device is in the SR mode and the PASR is enabled, the memory device is configured to skip, for each bank, the internal refreshing of each segment of that bank when either
the corresponding segment mask bit indicates that the refresh is disabled for that segment, or
the corresponding bank mask bit indicates that the refresh is disabled for that bank.
30. The apparatus of claim 25 ,
wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments,
wherein the PAR mask register includes a plurality of bank mask bits and a plurality of segment mask bits, each bank mask bit corresponding to a bank and indicating whether a refresh is enabled or disabled for the corresponding bank, and each segment mask bit corresponding to a segment and indicating whether a refresh is enabled or disabled for the corresponding segment, and
wherein when the memory device is in the SR mode and the PASR is enabled, the memory device is configured to skip, for each bank, the internal refreshing of each segment of that bank when both
the corresponding segment mask bit indicates that the refresh is disabled for that segment, and
the corresponding bank mask bit indicates that the refresh is disabled for that bank.