Memory system for controlling nonvolatile memory

1. A memory system connectable to a host, the memory system comprising:

a nonvolatile memory including a first region and a second region, the first region including a first plurality of blocks, the second region including a second plurality of blocks, each of the first plurality of blocks and the second plurality of blocks being a unit for a data erase operation; and

a controller electrically connected to the nonvolatile memory and configured to:

manage a first logical address space and a second logical address space;

store first data into a first block of the first region;

generate a first logical-to-physical address translation table such that logical addresses of the first logical address space are mapped with physical addresses of the first plurality of blocks of the first region;

generate a second logical-to-physical address translation table such that logical addresses of the second logical address space are mapped with the physical addresses of the first plurality of blocks of the first region;

in response to receiving a read request from the host, the read request specifying a logical address of the second logical address space, read at least a part of the first data from the first region on the basis of the second logical-to-physical address translation table; and

in response to receiving a write request from the host, the write request specifying a logical address of the second logical address space,

write second data into a second block of the second region, the second data being not stored in the first region, and

update only the second logical-to-physical address translation table among the first logical-to-physical address translation table and the second logical-to-physical address translation table such that the logical address specified by the write request is mapped with a physical address of the second block of the second region.

2. The memory system according to claim 1 , wherein

the controller is further configured to:

manage a first physical-to-physical address translation table; and

in a case where the first data is moved to a third block of the first region, update the first physical-to-physical address translation table such that, both in the first logical-to-physical address translation table and in the second logical-to-physical address translation table, a logical address associated with the first data is mapped with a physical address of the third block of the first region, without updating the first logical-to-physical address translation table and the second logical-to-physical address translation table.

3. The memory system according to claim 2 , wherein

the controller is configured to move the first data from the first block to the third block in a first refresh operation.

4. The memory system according to claim 3 , wherein

the controller is further configured to perform a second refresh operation in which the controller:

reads the first data from the first block;

perform an error correction operation to the read first data;

perform the data erase operation to the first block; and

writes the error-corrected first data into the data-erased first block.

5. The memory system according to claim 4 , wherein

the controller is configured to:

perform the second refresh operation in a case where a bit error rate of the first block is lower than a threshold; and

perform the first refresh operation in a case where the bit error rate of the first block is equal to or higher than the threshold.

6. The memory system according to claim 1 , wherein

the controller is configured to:

store the first data into the first block of the first region in a first write mode; and

write the second data into the second block of the second region in a second write mode, wherein

the number of bits stored in one memory cell in the first write mode is smaller than the number of bits stored in one memory cell in the second write mode.

7. The memory system according to claim 1 , wherein

the first logical address space is a first namespace and the second logical address space is a second namespace.

8. The memory system according to claim 1 , wherein

the number of blocks of the first region is smaller than the number of blocks corresponding to the logical addresses of the first logical address space.

9. The memory system according to claim 1 , wherein

the number of blocks of the first region is smaller than the number of blocks of the second region.

10. The memory system according to claim 1 , wherein

the controller is further configured to,

after storing the first data into the first block of the first region, inhibit a write access from the host to the first logical address space.

11. A method of controlling a nonvolatile memory including a first region and a second region, the first region including a first plurality of blocks, the second region including a second plurality of blocks, each of the first plurality of blocks and the second plurality of blocks being a unit for a data erase operation, the method comprising:

managing a first logical address space and a second logical address space;

storing first data into a first block of the first region;

generating a first logical-to-physical address translation table such that logical addresses of the first logical address space are mapped with physical addresses of the first plurality of blocks of the first region;

generating a second logical-to-physical address translation table such that logical addresses of the second logical address space are mapped with the physical addresses of the first plurality of blocks of the first region;

in response to receiving a read request from a host, the read request specifying a logical address of the second logical address space, reading at least a part of the first data from the first region on the basis of the second logical-to-physical address translation table; and

in response to receiving a write request from the host, the write request specifying a logical address of the second logical address space,

writing second data into a second block of the second region, the second data being not stored in the first region, and

updating only the second logical-to-physical address translation table among the first logical-to-physical address translation table and the second logical-to-physical address translation table such that the logical address specified by the write request is mapped with a physical address of the second block of the second region.

12. The method according to claim 11 , further comprising:

managing a first physical-to-physical address translation table; and

in a case where the first data is moved to a third block of the first region, updating the first physical-to-physical address translation table such that, both in the first logical-to-physical address translation table and in the second logical-to-physical address translation table, a logical address associated with the first data is mapped with a physical address of the third block of the first region, without updating the first logical-to-physical address translation table and the second logical-to-physical address translation table.

13. The method according to claim 12 , wherein

the first data are moved from the first block to the third block in a first refresh operation.

14. The method according to claim 13 , further comprising performing a second refresh operation, wherein the performing the second refresh operation includes:

reading the first data from the first block;

performing an error correction operation to the read first data;

performing the data erase operation to the first block; and

writing the error-corrected first data into the data-erased first block.

15. The method according to claim 14 , wherein

the second refresh operation is performed in a case where a bit error rate of the first block is lower than a threshold; and

the first refresh operation is performed in a case where the bit error rate of the first block is equal to or higher than the threshold.

16. The method according to claim 11 , wherein

the storing includes storing the first data into the first block of the first region in a first write mode; and

the writing includes writing the second data into the second block of the second region in a second write mode, wherein

the number of bits stored in one memory cell in the first write mode is smaller than the number of bits stored in one memory cell in the second write mode.

17. The method according to claim 11 , wherein

the first logical address space is a first namespace and the second logical address space is a second namespace.

18. The method according to claim 11 , wherein

the number of blocks of the first region is smaller than the number of blocks corresponding to the logical addresses of the first logical address space.

19. The method according to claim 11 , wherein

the number of blocks of the first region is smaller than the number of blocks of the second region.

20. The method according to claim 11 , further comprising,

after storing the first data into the first block of the first region, inhibiting a write access from the host to the first logical address space.