Semiconductor integrated circuit adapted to output pass/fail results of internal operations
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
1. An operating method of a semiconductor integrated circuit comprising:
starting a first data program operation to a first page;
starting a second data program operation to a second page after starting the first data program operation;
internally holding a pass/fail result of the first data program operation after the termination thereof;
internally holding a pass/fail result of the second data program operation after the termination thereof; and
in response to an input of a status read command, outputting to an outside of the semiconductor integrated circuit both the pass/fail result of the first data program operation and the pass/fail result of the second data program operation after the termination of the first and second data program operations.
2. The operating method according to claim 1 , wherein the first data program operation and the second data program operation are performed in succession.
3. The operating method according to claim 1 , wherein the first data program operation starts in response to an input of a first command sequence including a first command, a first address, first data, and a second command different from the first command.
4. The operating method according to claim 3 , wherein the second data program operation starts in response to an input of a second command sequence including the first command, a second address, second data, and the second command.
5. The operating method according to claim 4 , further comprising:
starting a third data program operation to a third page in response to an input of a third command sequence including the first command, a third address, third data, and a third command different from the second command, after starting the second data program operation,
wherein the third page is the final page in a data program sequence.
6. The operating method according to claim 4 , further comprising:
starting a third data program operation to a third page in response to an input of a third command sequence including the first command, a third address, third data, and a third command different from the second command, after starting the second data program operation;
wherein the outputting both the pass/fail result of the first data program operation and the pass/fail result of the second data program operation are before the termination of the third data program operation.
7. The operating method according to claim 4 , further comprising:
starting a third data program operation to a third page in response to an input of a third command sequence including the first command, a third address, third data, and a third command different from the second command, after starting the second data program operation;
wherein in response to an input of the status read command, outputting both the pass/fail result of the second data program operation and the pass/fail result of the third data program operation after the termination of the third data program operation.
8. The operating method according to claim 7 , wherein the second data program operation and the third data program operation are performed in succession.
9. The operating method according to claim 1 , wherein the outputting both the pass/fail result of the first data program operation and the pass/fail result of the second data program operation are from a first I/O pad and a second I/O pad respectively.
10. The operating method according to claim 1 , further comprising:
in response to the input of the status read command, also outputting to the outside of the semiconductor integrated circuit both a first ready/busy signal and a second ready/busy signal.
11. The operating method according to claim 3 , further comprising:
in response to the input of the status read command, also outputting to the outside of the semiconductor integrated circuit both a first ready/busy signal and a second ready/busy signal
wherein the first command is valid when the first ready/busy signal is ready and the second ready/busy signal is busy.
12. The operating method according to claim 3 , further comprising:
in response to the input of the status read command, also outputting to the outside of the semiconductor integrated circuit both a first ready/busy signal and a second ready/busy signal,
wherein a reading-related command and an erasing-related command are inhibited or ignored when the first ready/busy signal is ready and the second ready-busy signal is busy.
13. The operating method according to claim 3 , further comprising:
inputting the first data to data cache circuits;
transferring the first data from the data cache circuits to a sense latch circuits; and
programming the first data latched in the sense latch circuits into first memory cells.
14. The operating method according to claim 4 , further comprising:
inputting the first data to data cache circuits;
transferring the first data from the data cache circuits to sense latch circuits;
programming the first data latched in the sense latch circuits into first memory cells; and
inputting the second data to the data cache circuits during the programming the first data into the first memory cells.
15. The operating method according to claim 5 , further comprising:
inputting the third data to data cache circuits during the programming the second data into second memory cells;
transferring the third data from the data cache circuits to sense latch circuits; and
programming the third data latched in the sense latch circuits into third memory cells.
16. The operating method according to claim 13 , wherein the first memory cells are placed in two memory cell arrays.
17. The operating method according to claim 13 , wherein the first memory cells are placed in a memory cell array.
18. The operating method according to claim 13 , wherein gates of the first memory cells are connected to each other.
19. The operating method according to claim 13 , wherein one of the data cache circuits includes two inverters.
20. The operating method according to claim 13 , wherein one of the sense latch circuits includes two inverters.