Array substrate, display panel and display device

1. An array substrate, comprising:

a plurality of pixel structures in a display area of the array substrate and arranged in rows and columns;

a plurality of first driving signal wires extending in a row direction; and

a plurality of leads extending in a column direction crossing the row direction, the plurality of leads comprising a plurality of first-type leads and at least one second-type lead,

wherein a respective one of the plurality of first driving signal wires is electrically connected to a respective row of the plurality of pixel structures and is electrically connected to a respective one of the plurality of first-type leads via a first electrical connection point,

wherein the at least one second-type lead is electrically connected to a respective one of the plurality of first driving signal wires via a second electrical connection point and is connected in parallel with a corresponding first-type lead of the plurality of first-type leads electrically connected to the respective one of the plurality of first driving signal wires, and

wherein the plurality of pixel structures are arranged in an M×N array, a number of the first-type leads is M, a number of the at least one second-type leads is (2N−M), a relationship between M and N satisfies 2N>M>N, and both M and N are positive integers greater than 1.

2. The array substrate according to claim 1 , wherein the corresponding first-type lead and the at least one second-type lead connected in parallel are in a same column or different columns of the pixel structures.

3. The array substrate according to claim 1 , wherein respective columns of the plurality of pixel structures comprise a same number of the plurality of leads.

4. The array substrate according to claim 1 , further comprising:

at least one first connection wire; and

at least one second connection wire,

wherein one end of each of the first-type lead and the at least one second-type lead connected in parallel are electrically connected via the at least one first connecting wire, and

wherein another end of each of the first-type lead and the at least one second-type lead connected in parallel are electrically connected via the at least one second connection wire.

5. The array substrate according to claim 1 , further comprising:

a fan-out area in a non-display area of the array substrate,

wherein the fan-out area comprises a plurality of first fan-out wires, and

wherein a respective one of the plurality of first fan-out wires is electrically connected to a respective one of the plurality of first-type leads.

6. The array substrate according to claim 5 , further comprising:

at least one first driving circuit,

wherein the at least one first driving circuit is electrically connected to the plurality of first fan-out wires to transmit driving signals to the plurality of first driving signal wires, and

wherein each of the plurality of first-type leads has substantially a same transmission load.

7. The array substrate according to claim 6 ,

wherein each of the plurality of first-type leads comprises a first sub-lead portion and a second sub-lead portion spaced apart from each other,

wherein the first sub-lead portion is electrically connected to a respective one of the plurality of first driving signal wires via the first electrical connection point,

wherein the second sub-lead portion is floating,

wherein the at least one second-type lead comprises a third sub-lead portion and a fourth sub-lead portion spaced apart from each other,

wherein the third sub-lead portion is electrically connected to a respective one of the plurality of first driving signal wires via the second electrical connection point,

wherein the fourth sub-lead portion is floating, and

wherein the third sub-lead portion of the at least one second-type lead is connected in parallel with the first sub-lead portion of the respective one of the plurality of first-type leads.

8. The array substrate according to claim 7 ,

wherein one of the plurality of first driving signal wires has a first orthographic projection on the array substrate,

wherein a gap between the first sub-lead portion and the second sub-lead portion of a corresponding first-type lead electrically connected to the first driving signal wire has a second orthographic projection on the array substrate, and

wherein the first orthographic projection overlaps the second orthographic projection.

9. The array substrate according to claim 7 ,

wherein one of the plurality of first driving signal wires has a first orthographic projection on the array substrate,

wherein a gap between the third sub-lead portion and the fourth sub-lead portion of the at least one second-type lead electrically connected to the first driving signal wire has a third orthographic projection on the array substrate, and

wherein the first orthographic projection overlaps the third orthographic projection.

10. The array substrate according to claim 7 ,

wherein the plurality of pixel structures comprise a middle column portion and edge column portions on both sides with respect to the at least one first driving circuit,

wherein a maximum distance between the first electrical connection points at the edge column portions on both sides and the at least one first driving circuit comprises a first distance,

wherein a minimum distance between the first electrical connection points at the middle column portion and the at least one first driving circuit comprises a second distance,

wherein the first distance is less than the second distance, and

wherein lengths of the first fan-out wires corresponding to the edge column portions on both sides are longer than lengths of the first fan-out wires corresponding to the middle column portion.

11. The array substrate according to claim 6 , further comprising:

a plurality of second driving signal wires extending in the column direction,

wherein a respective one of the plurality of second driving signal wires is electrically connected to a respective column of the plurality of pixel structures.

12. The array substrate according to claim 11 ,

wherein the fan-out area further comprises a plurality of second fan-out wires,

wherein a respective one of the plurality of second fan-out wires is electrically connected to a respective one of the plurality of second driving signal wires,

wherein the array substrate further comprises at least one second driving circuit, and

wherein the plurality of second fan-out wires are electrically connected to the at least one second driving circuit.

13. The array substrate according to claim 12 , wherein the at least one first driving circuit and the at least one second driving circuit are integrated into a same driving circuit.

14. The array substrate according to claim 11 ,

wherein the first driving signal wire is selected from one of a data line and a gate line, and

wherein the second driving signal wire is selected from another of the data line and the gate line.

15. A display panel comprising the array substrate according to claim 1 .

16. A display device comprising the array substrate according to claim 1 .

17. The array substrate according to claim 1 ,

wherein a plurality of the first electrical connection points are substantially in a straight line in a first direction,

wherein the first direction crosses the row direction and the column direction respectively.

18. The array substrate according to claim 17 , wherein a plurality of the second electrical connection points are substantially in another straight line in a direction parallel to the first direction.

19. The array substrate according to claim 17 ,

wherein a plurality of the second electrical connection points are substantially in a straight line in a second direction,

wherein the second direction crosses the row direction, the column direction and the first direction respectively.