Channel access mechanisms for DRS transmission and PDCCH monitoring for NR-U networks
An apparatus for a UE includes processing circuitry coupled to memory. To configure the UE for shared spectrum channel access in a 5G-NR system, the processing circuitry is to decode a synchronization signal (SS)/physical broadcast channel (PBCH) block (SSB) to obtain a master information block (MIB). System information block 1 (SIB1) configuration information is determined using the MIB. The SIB1 configuration information is used to configure a Type 0 PDCCH common search space (CSS) set (CORESET). The processing circuitry is to monitor for a PDCCH in the Type 0 PDCCH CSS set over slots that include Type 0 PDCCH monitoring occasions. At least one of the slots includes the SSB and the CORESET multiplexed according to multiplexing pattern 1. The PDCCH is detected in at least one of the Type 0 PDCCH monitoring occasions. A SIB1 is decoded using downlink control information (DCI) received via the detected PDCCH.
1. An apparatus for a user equipment (UE), the apparatus comprising:
processing circuitry, wherein to configure the UE for shared spectrum channel access in a Fifth Generation New Radio (5G-NR) system, the processing circuitry is to:
decode a synchronization signal (SS)/physical broadcast channel (PBCH) block (SSB) to obtain a master information block (MIB);
determine system information block 1 (SIB1) configuration information using the MIB, the SIB1 configuration information to configure a Type 0 physical downlink control channel (PDCCH) common search space (CSS) set (CORESET);
determine a slot number of at least one slot of slots, wherein the at least one slot includes the SSB and the CORESET;
wherein the determining of the slot number is based on an SS/PBCH block index of the SSB and further based on the SSB and CORESET in the at least one slot of slots being multiplexed according to multiplexing pattern 1;
monitor for a PDCCH in the Type 0 PDCCH CSS set over the at least one slot associated with the slot number, the at least one slot of the slots including the SSB and the CORESET multiplexed according to multiplexing pattern 1;
detect the PDCCH in at least one of the Type 0 PDCCH monitoring occasions;
and decode a SIB 1 using downlink control information (DCI) received via the detected PDCCH;
and memory coupled to the processing circuitry and configured to store the SSB.
2. The apparatus of claim 1 , wherein the processing circuitry is further to:
determine the slot number of the at least one slot of the slots further based on a time offset value, the time offset value corresponding to an index of a first symbol of the CORESET in the at least one of the slots.
3. The apparatus of claim 2 , wherein the at least one slot of the slots comprises two neighboring slots.
4. The apparatus of claim 2 , wherein the slot number of the at least one slot is determined as n 0 =(O·2 μ +└ī·M┘)mod N slot frame,μ , where O is the time offset value, M is a factor corresponding to the time offset value, and μ is an integer selected from a set of integers including {0,1,2,3}, and ī is the SS/PBCH block index.
5. The apparatus of claim 1 , further comprising transceiver circuitry coupled to the processing circuitry; and, one or more antennas coupled to the transceiver circuitry.
6. A non-transitory computer-readable storage medium that stores instructions for execution by one or more processors of a user equipment (UE), the instructions to configure the UE for shared spectrum channel access in a Fifth Generation New Radio (5G-NR) system, and to cause the UE to perform operations comprising:
decoding a synchronization signal (SS)/physical broadcast channel (PBCH) block (SSB) to obtain a master information block (MIB);
determining system information block 1 (SIB1) configuration information using the MIB, the SIB1 configuration information to configure a Type 0 physical downlink control channel (PDCCH) common search space (CSS) set (CORESET);
determine a slot number of at least one slot of slots, wherein the at least one slot includes the SSB and the CORESET;
wherein the determining of the slot number is based on an SS/PBCH block index of the SSB and further based on the SSB and CORESET in the at least one slot of slots being multiplexed according to multiplexing pattern 1;
monitoring for a PDCCH in the Type 0 PDCCH CSS set over the at least one slot associated with the slot number, the at least one slot of the slots including the SSB and the CORESET multiplexed according to multiplexing pattern 1;
detecting the PDCCH in at least one of the Type 0 PDCCH monitoring occasions; and
decoding a SIB1 using downlink control information (DCI) received via the detected PDCCH.
7. The non-transitory computer-readable storage medium of claim 6 , the operations further comprising:
determining the slot number of the at least one slot of the slots further based on a time offset value, the time offset value corresponding to an index of a first symbol of the CORESET in the at least one of the slots.
8. The non-transitory computer-readable storage medium of claim 7 , wherein the at least one slot of the slots comprises two neighboring slots.
9. The non-transitory computer-readable storage medium of claim 7 , wherein the slot number of the at least one slot is determined as
n 0 =(O·2 μ +└ī·M┘)mod N slot frame,μ , where O is the time offset value, M is a factor corresponding to the time offset value, and μ is an integer selected from a set of integers including {0,1,2,3}, and ī is the SS/PBCH block index.