IP Library Granted Patent US 11,658,238
Granted Patent B2
US 11,658,238 · App. 16/912,439 · Granted May 23, 2023

Semiconductor device

Inventors: Katsutoshi Sugawara (Tokyo, JP); Yasuhiro Kagawa (Tokyo, JP); Yutaka Fukui (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H01L29/7815H01L29/66068H01L29/7811H01L29/7813H03K17/687H01L29/0623H01L29/0696H01L29/1608H01L29/4238
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,658,238
App. No.
16/912,439
Granted
May 23, 2023
Kind
B2
Abstract

A semiconductor device includes a trench-type switching element formed in an active region and a trench-type current sense element formed in a current sense region. Below a trench in which a gate electrode of the switching element is embedded, a trench in which a gate electrode of the current sense element is embedded, and a trench formed at the boundary portion between the active region and the current sense region, protective layers are formed, respectively. The protective layer at the boundary portion between the active region and the current sense region has a divided portion that is divided in a direction from the active region to the current sense region.

Claims (61)

1. A semiconductor device comprising:

a semiconductor layer in which a first conductivity-type drift layer is formed;

a trench-type switching element in which a gate electrode is embedded in a first trench formed in the semiconductor layer to reach the drift layer;

a trench-type current sense element in which a gate electrode is embedded in a second trench formed in the semiconductor layer to reach the drift layer;

a third trench configured to be formed in the semiconductor layer at a boundary portion between an active region where the switching element is formed and a current sense region where the current sense element is formed, and reach the drift layer;

a second conductivity-type first protective layer formed directly below the first trench in the drift layer;

a second conductivity-type second protective layer formed directly below the second trench in the drift layer; and

a second conductivity-type third protective layer formed directly below the third trench in the drift layer such that a portion of the third protective layer overlaps the third trench, wherein

the third protective layer has a divided portion divided in a first direction from the active region to the current sense region, and

first end surfaces of the third protective layer facing each other form the divided portion, and second end surfaces of the third protective layer opposite to the first end surfaces are positioned between opposing sidewalls of the third trench.

2. The semiconductor device according to claim 1 , wherein a plurality of the divided portion of the third protective layer are provided along the first direction.

3. The semiconductor device according to claim 1 , further comprising:

a fourth trench configured to be formed in the semiconductor layer in an outer peripheral region provided around the active region and the current sense region, and reach the drift layer; and

a second conductivity-type fourth protective layer formed below the fourth trench in the drift layer.

4. The semiconductor device according to claim 1 , wherein the second end surfaces of the third protective layer opposite to the divided portion are vertically aligned with the opposing sidewalls of the third trench.

5. A semiconductor device comprising:

a semiconductor layer in which a first conductivity-type drift layer is formed;

a trench-type switching element in which a gate electrode is embedded in a first trench formed in the semiconductor layer to reach the drift layer;

a trench-type current sense element in which a gate electrode is embedded in a second trench formed in the semiconductor layer to reach the drift layer;

a third trench configured to be formed in the semiconductor layer at a boundary portion between an active region where the switching element is formed and a current sense region where the current sense element is formed, and reach the drift layer;

a second conductivity-type first protective layer formed below the first trench in the drift layer;

a second conductivity-type second protective layer formed below the second trench in the drift layer; and

a second conductivity-type third protective layer formed below the third trench in the drift layer, wherein

the third protective layer has a divided portion divided in a first direction from the active region to the current sense region, and

a width of the divided portion of the third protective layer is equal to or less than an interval of the first trenches and an interval of the second trenches.

6. The semiconductor device according to claim 5 , wherein

the gate electrode in the switching element is included among a plurality of gate electrodes in the switching element,

the first trench is included among a plurality of first trenches formed in the semiconductor layer to reach the drift layer in the switching element,

the gate electrodes in the switching element are respectively embedded in the first trenches,

the gate electrode in the current sense element is included among a plurality of gate electrodes in the current sense element,

the second trench is included among a plurality of second trenches formed in the semiconductor layer to reach the drift layer in the current sense element,

the gate electrodes in the current sense element are respectively embedded in the first trenches,

the first protective layer and the second protective layer are formed below the second trenches, and

the width of the divided portion of the third protective layer is equal to or less than an interval between adjacent ones of the first trenches and an interval between adjacent ones of the second trenches.

7. The semiconductor device according to claim 6 , wherein the width of the divided portion of the third protective layer, the interval between adjacent ones of the first trenches and the interval between adjacent ones of the second trenches are each measured in the first direction.

8. A semiconductor device comprising:

a semiconductor layer in which a first conductivity-type drift layer is formed;

a trench-type switching element in which a gate electrode is embedded in a first trench formed in the semiconductor layer to reach the drift layer;

a trench-type current sense element in which a gate electrode is embedded in a second trench formed in the semiconductor layer to reach the drift layer;

a third trench configured to be formed in the semiconductor layer at a boundary portion between an active region where the switching element is formed and a current sense region where the current sense element is formed, and reach the drift layer;

a second conductivity-type first protective layer formed below the first trench in the drift layer;

a second conductivity-type second protective layer formed below the second trench in the drift layer; and

a second conductivity-type third protective layer formed directly below the third trench in the drift layer such that a portion of the third protective layer overlaps the third trench, wherein

the third protective layer has a divided portion divided in a first direction from the active region to the current sense region, and

in the third trench, the semiconductor layer having a mesa shape and extending upward from a bottom surface of the third trench is formed on the divided portion of the third protective layer.

9. The semiconductor device according to claim 8 , wherein a plurality of the divided portions of the third protective layer and a plurality of the semiconductor layers having the mesa shape are provided along the first direction.

10. The semiconductor device according to claim 9 , wherein the divided portions of the third protective layer and the semiconductor layers having the mesa shape are provided at equal intervals along the first direction.

11. A semiconductor device comprising:

a semiconductor layer in which a first conductivity-type drift layer is formed;

a trench-type switching element in which a gate electrode is embedded in a first trench formed in the semiconductor layer to reach the drift layer;

a trench-type current sense element in which a gate electrode is embedded in a second trench formed in the semiconductor layer to reach the drift layer;

a third trench configured to be formed in the semiconductor layer at a boundary portion between an active region where the switching element is formed and a current sense region where the current sense element is formed, and reach the drift layer;

a second conductivity-type first protective layer formed below the first trench in the drift layer;

a second conductivity-type second protective layer formed below the second trench in the drift layer; and

a second conductivity-type third protective layer formed below the third trench in the drift layer, wherein

the third protective layer has a divided portion divided in a first direction from the active region to the current sense region, and

in the third trench, a plurality of the semiconductor layers having the mesa shape are formed side by side in a second direction perpendicular to the first direction.

12. The semiconductor device according to claim 11 , wherein a length of the semiconductor layer having the mesa shape in the first direction is longer than a length in the second direction.

13. The semiconductor device according to claim 12 , wherein the semiconductor layers having the mesa shape are provided in the second direction at the same interval as an interval of cells of the switching element.

14. The semiconductor device according to claim 11 , wherein the plurality of semiconductor layers having the mesa shape extend upward from a bottom surface of the third trench.

15. The semiconductor device according to claim 11 , wherein the plurality of the semiconductor layers having the mesa shape form a plurality of mesa shaped structures extending upward from a bottom surface of the third trench, the plurality of mesa shaped structures being formed side by side in the second direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2020
From: SUGAWARA, KATSUTOSHI; KAGAWA, YASUHIRO; FUKUI, YUTAKA
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 053043/0414 →
Priority Claims (1)
JP JP2019-170127 · Sep 19, 2019 · national
Continuity (1)
Related Publication 20210091220A1 · Mar 25, 2021