SOURCE OR DRAIN STRUCTURES WITH HIGH SURFACE GERMANIUM CONCENTRATION
Integrated circuit structures having high surface germanium concentrations are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure has an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure has an epitaxial structure embedded in the fin at the second side of the gate stack. Each of the epitaxial structures of the first and second source or drain structures includes silicon, germanium and boron, the germanium having an atomic concentration of greater than 55% at a top surface of each of the epitaxial structures of the first and second source or drain structures.
1 . An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack;
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each of the epitaxial structures of the first and second source or drain structures comprising silicon, germanium and boron, the germanium having an atomic concentration of greater than 55% at a top surface of each of the epitaxial structures of the first and second source or drain structures; and
a metal silicide layer on and in direct contact with the top surface of each of the epitaxial structures of the first and second source or drain structures.
2 . The integrated circuit structure of claim 1 , wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition substantially the same as the composition of the each of the epitaxial structures at the top surface of each of the epitaxial structures.
3 . The integrated circuit structure of claim 1 , wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition with an atomic concentration of germanium of less than 10%.
4 . The integrated circuit structure of claim 3 , wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition with an atomic concentration of germanium of less than 5%.
5 . The integrated circuit structure of claim 1 , wherein the lower fin portion includes a portion of an underlying bulk single crystalline silicon substrate.
6 . The integrated circuit structure of claim 1 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.
7 . The integrated circuit structure of claim 1 , further comprising:
a first conductive contact on a first portion of the metal silicide layer on the epitaxial structure of the first source or drain structure; and
a second conductive contact on a second portion of the metal silicide layer on the epitaxial structure of the second source or drain structure.
8 . An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer;
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer on the lower semiconductor layer, wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises silicon, germanium and boron, the germanium having an atomic concentration of greater than 55% at a top surface of the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures, and wherein the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises silicon, germanium and boron, the germanium having an atomic concentration of less than 10%; and
a metal silicide layer in an opening of the capping semiconductor layer, the metal silicide layer in direct contact with the top surface of the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures.
9 . The integrated circuit structure of claim 8 , wherein the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises the germanium having an atomic concentration of less than 5%.
10 . The integrated circuit structure of claim 9 , wherein the capping semiconductor layer of each of the epitaxial structures of the first and second source or drain structures comprises the boron having an atomic concentration of greater than 5E20 cm −3 .
11 . The integrated circuit structure of claim 8 , wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition substantially the same as the composition of the lower semiconductor layer at the top surface of the lower semiconductor layer.
12 . The integrated circuit structure of claim 8 , wherein the metal silicide layer is a silicide of a silicon germanium layer having a composition substantially the same as the composition of the capping semiconductor layer.
13 . The integrated circuit structure of claim 8 , wherein the lower fin portion includes a portion of an underlying bulk single crystalline silicon substrate.
14 . The integrated circuit structure of claim 8 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.
15 . The integrated circuit structure of claim 8 , further comprising:
a first conductive contact on a first portion of the metal silicide layer on the lower semiconductor layer of the epitaxial structure of the first source or drain structure; and
a second conductive contact on a second portion of the metal silicide layer on the lower semiconductor layer of the epitaxial structure of the second source or drain structure.
16 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack;
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each of the epitaxial structures of the first and second source or drain structures comprising silicon, germanium and boron, the germanium having an atomic concentration of greater than 55% at a top surface of each of the epitaxial structures of the first and second source or drain structures; and
a metal silicide layer on and in direct contact with the top surface of each of the epitaxial structures of the first and second source or drain structures.
17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.
18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19 . The computing device of claim 16 , further comprising:
a camera coupled to the board.
20 . The computing device of claim 16 , further comprising:
a battery coupled to the board.
21 . The computing device of claim 16 , further comprising:
an antenna coupled to the board.
22 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.