Integrated simulator and analysis and optimization engine

1. A system, comprising:

one or more processors configured to:

access circuit information of a circuit;

perform, using an analysis and optimization engine, power analysis and optimization on the circuit to generate an optimized circuit, the power analysis and optimization being performed using an input pattern;

perform, using a simulator, a simulation on at least a portion of an optimized circuit, the simulation being performed using the input pattern used in the power analysis and optimization; and

output a simulation result to the analysis and optimization engine;

wherein the analysis and optimization engine and the simulator are integrated; and

one or more memories coupled to the one or more processors, configured to provide the one or more processors with instructions.

2. The system of claim 1 , wherein the analysis and optimization engine communicates with the simulator via application programming interfaces (APIs).

3. The system of claim 1 , wherein the input pattern is extracted from an initial project data associated with the circuit, derived from the initial project data associated with the circuit, or generated as a randomized pattern.

4. The system of claim 1 , wherein the input pattern is a randomized pattern whose characteristics are determined based on a circuit type associated with the circuit.

5. The system of claim 1 , wherein:

the input pattern is a randomized pattern whose characteristics are determined based on a circuit type associated with the circuit; and

the circuit type is determined by analyzing the circuit or specified by a user via a user interface.

6. The system of claim 1 , wherein the simulation is performed incrementally in time, area, or both.

7. The system of claim 1 , wherein to perform the simulation includes to:

define a plurality of localized window areas corresponding to respective ones of a plurality of optimization moves;

perform a plurality of simulations corresponding to the plurality of localized window areas; and

select one or more optimization moves among the plurality of optimization moves based on results of the plurality of simulations.

8. The system of claim 1 , where the simulation is event-driven.

9. The system of claim 1 , where the simulation is event-driven, and simulation events are stored on a hierarchical set of time wheels.

10. The system of claim 1 , wherein in response to an anti-event, the simulator is configured to invalidate a previous event specified by the anti-event.

11. The system of claim 1 , wherein the simulation is performed by multiple threads.

12. A method, comprising:

accessing circuit information of a circuit;

performing, using an analysis and optimization engine, power analysis and optimization on the circuit to generate an optimized circuit, the power analysis and optimization being performed using an input pattern;

performing, using a simulator, a simulation on at least a portion of an optimized circuit, the simulation being performed using the input pattern used in the power analysis and optimization; and

outputting a simulation result to the analysis and optimization engine; wherein the analysis and optimization engine and the simulator are integrated.

13. The method of claim 12 , wherein the analysis and optimization engine communicates with the simulator via application programming interfaces (APIs).

14. The method of claim 12 , wherein the input pattern is extracted from an initial project data associated with the circuit, derived from the initial project data associated with the circuit, or generated as a randomized pattern.

15. The method of claim 12 , wherein the input pattern is a randomized pattern whose characteristics are determined based on a circuit type associated with the circuit.

16. The method of claim 12 , wherein:

the input pattern is a randomized pattern whose characteristics are determined based on a circuit type associated with the circuit; and

the circuit type is determined by analyzing the circuit or specified by a user via a user interface.

17. The method of claim 12 , wherein the simulation is performed incrementally in time, area, or both.

18. The method of claim 12 , wherein performing the simulation includes:

defining a plurality of localized window areas corresponding to respective ones of a plurality of optimization moves;

performing a plurality of simulations corresponding to the plurality of localized window areas; and

selecting one or more optimization moves among the plurality of optimization moves based on results of the plurality of simulations.

19. The method of claim 12 , where the simulation is event-driven.

20. The method of claim 12 , where the simulation is event-driven, and simulation events are stored on a hierarchical set of time wheels.

21. The method of claim 12 , wherein in response to an anti-event, the simulator is configured to invalidate a previous event specified by the anti-event.

22. The method of claim 12 , wherein the simulation is performed by multiple threads.

23. A computer program product embodied in a non-transitory computer readable medium and comprising computer instructions for:

accessing circuit information of a circuit;

performing, using an analysis and optimization engine, power analysis and optimization on the circuit to generate an optimized circuit, the power analysis and optimization being performed using an input pattern;

performing, using a simulator, a simulation on at least a portion of an optimized circuit, the simulation being performed using the input pattern used in the power analysis and optimization; and

outputting a simulation result to the analysis and optimization engine; wherein the analysis and optimization engine and the simulator are integrated.