Streaming engine with early and late address and loop count registers to track architectural state
A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.
1. A device comprising:
a processing core;
a memory; and
a memory controller coupled to the processing core and to the memory, wherein the memory controller includes:
a first address generator configured to generate a first set of addresses;
a memory interface coupled to the memory and configured to retrieve a set of data elements based on the first set of addresses;
a buffer configured to store the set of data elements;
a holding register coupled to the processing core and configured to store a first data element of the set of data elements; and
a second address generator configured to generate an address that corresponds to a second data element of the set of data elements;
wherein the memory controller is configured to:
receive a read instruction from the processing core; and
based on the read instruction:
provide the first data element to the processing core;
cause the second address generator to generate the address; and
cause the second data element to be provided from the buffer to the holding register and to replace the first data element.
2. The device of claim 1 , wherein the first address generator includes:
a plurality of loop count registers;
a plurality of adders coupled to the plurality of loop count registers;
a plurality of comparators coupled to the plurality of adders and each configured to:
compare an output of a respective adder of the plurality of adders to a threshold; and
based on the output of the respective adder of the plurality of adders equaling the threshold, provide a loop end signal configured to cause an iteration of a next higher loop.
3. The device of claim 2 , wherein:
the first address generator includes a plurality of registers configured to store the thresholds for the plurality of comparators; and
the thresholds are based on a stream definition template.
4. The device of claim 2 , wherein the first address generator includes:
a plurality of multipliers coupled to the plurality of adders and each configured to multiply the output of a respective adder of the plurality of adders by a data element size to determine an address of the first set of addresses.
5. The device of claim 2 , wherein:
the processing core has a debugger function; and
values of the plurality of loop count registers are accessible by the processing core via the debugger function.
6. The device of claim 1 further comprising an address register coupled to the first address generator and the memory interface and configured to store a first address of the first set of addresses that corresponds to a next data element to be retrieved from the memory by the memory interface.
7. The device of claim 1 , wherein the memory includes a level two (L2) cache and the memory interface is configured to retrieve the set of data elements directly from the L2 cache.
8. The device of claim 1 comprising a level one (L1) cache and a level two (L2) cache, wherein:
the memory includes the L2 cache; and
the memory interface is configured to retrieve the set of data elements from the L2 cache via a data path that does not include the L1 cache.
9. The device of claim 1 , wherein the memory controller includes a data formatting circuit coupled between the buffer and the holding register and configured to format a subset of the set of data elements that includes the second data element such that the formatted subset of the set of data elements is stored in the holding register.
10. The device of claim 9 , wherein the data formatting circuit is configured to format the subset of the set of data elements according to a stream definition template.
11. The device of claim 9 further comprising a reference queue coupled to the data formatting circuit and configured to store, for each element of the set of data elements:
an address at which the element is stored in the buffer; and
a format for the element to be applied by the data formatting circuit.
12. The device of claim 1 , wherein the buffer is a first-in-first-out buffer.
13. A device comprising:
a processing core;
a level one (L1) cache memory;
a level two (L2) cache memory; and
a memory controller coupled to the processing core and to the L2 cache memory, wherein the memory controller includes:
a first address generator configured to generate a first set of addresses;
a memory interface coupled to the L2 cache memory and configured to retrieve a set of data elements based on the first set of addresses from the L2 cache memory via a data path that does not include the L1 cache memory;
a buffer configured to store the set of data elements;
a holding register coupled to the processing core and configured to store a first data element;
a second address generator configured to generate an address associated with a second data element;
wherein the memory controller is configured to:
provide the first data element from the holding register to the processing core; and
based on the first data element being provided:
cause the second address generator to generate the address; and
based on the address, cause the second data element to be provided from the buffer to the holding register and to replace the first data element.
14. The device of claim 13 , wherein the first address generator includes:
a plurality of loop count registers;
a plurality of adders coupled to the plurality of loop count registers;
a plurality of comparators coupled to the plurality of adders and each configured to:
compare an output of a respective adder of the plurality of adders to a threshold; and
based on the output of the respective adder of the plurality of adders equaling the threshold, provide a loop end signal configured to cause an iteration of a next higher loop.
15. The device of claim 14 , wherein:
the first address generator includes a plurality of registers configured to store the thresholds for the plurality of comparators; and
the thresholds are based on a stream definition template.
16. The device of claim 15 , wherein the first address generator includes:
a plurality of multipliers coupled to the plurality of adders and each configured to multiply the output of a respective adder of the plurality of adders by a data element size to determine an address of the first set of addresses.
17. The device of claim 14 , wherein:
the processing core has a debugger function; and
values of the plurality of loop count registers are accessible by the processing core via the debugger function.
18. The device of claim 13 , wherein the memory controller includes a data formatting circuit coupled between the buffer and the holding register and configured to format a subset of the set of data elements that includes the second data element such that the formatted subset of the set of data elements is stored in the holding register.
19. The device of claim 18 , wherein the data formatting circuit is configured to format the subset of the set of data elements according to a stream definition template.
20. The device of claim 18 further comprising a reference queue coupled to the data formatting circuit and configured to store, for each element of the set of data elements:
an address at which the element is stored in the buffer; and
a format for the element to be applied by the data formatting circuit.