IP Library Granted Patent US 11,315,924
Granted Patent B2
US 11,315,924 · App. 16/917,778 · Granted Apr 26, 2022

Isolation structure for preventing unintentional merging of epitaxially grown source/drain

Inventors: Ta-Chun Lin (Hsinchu, TW); Kuan-Lin Yeh (Hsinchu, TW); Chun-Jun Lin (Hsinchu, TW); Kuo-Hua Pan (Hsinchu, TW); Mu-Chi Chiang (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L27/0924H01L21/762H01L21/76831H01L21/823814H01L21/823821H01L21/823842H01L21/823878H01L29/0649H01L29/66545H01L29/66553H01L29/66795H01L29/7851
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Quick Facts
Patent No.
US 11,315,924
App. No.
16/917,778
Granted
Apr 26, 2022
Kind
B2
Abstract

A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

Claims (52)

1. A device, comprising:

a first active region and a second active region disposed over a substrate;

a first source/drain component grown on the first active region;

a second source/drain component grown on the second active region;

an interlayer dielectric (ILD) disposed around the first source/drain component and the second source/drain component; and

an isolation structure extending vertically through the ILD and separating the first source/drain component from the second source/drain component, wherein an uppermost surface of the isolation structure is more elevated vertically than an uppermost surface of the first source/drain component.

2. The device of claim 1 , wherein the first source/drain component and the second source/drain component each has an asymmetrical profile in a cross-sectional view.

3. The device of claim 2 , wherein:

The first source/drain component and the second source/drain component each has a first outermost portion in a first horizontal side and a second outermost portion in a second horizontal side opposite the first horizontal side; and

a shape of the first outermost portion is different than a shape of the second outermost portion.

4. The device of claim 3 , wherein:

the shape of the first outermost portion resembles a line; and

the shape of the second outermost portion resembles a pointy tip.

5. The device of claim 1 , wherein at least one of the first source/drain component and the second source/drain component includes multiple epitaxially source/drain features that are merged together.

6. The device of claim 1 , wherein the isolation structure includes:

a dielectric liner that is in direct contact with the first source/drain component and the second source/drain component; and

a dielectric segment disposed over the dielectric liner.

7. The device of claim 6 , wherein the dielectric liner and the dielectric segment have different material compositions.

8. The device of claim 1 , wherein the device is a FinFET device.

9. The device of claim 1 , wherein the device is a Gate-All-Around (GAA) device.

10. A device, comprising:

a plurality of active regions disposed over a substrate;

a plurality of gate structures disposed over the active regions; and

a plurality of source/drains epitaxially grown over the active regions, respectively, wherein in a cross-sectional view defined by a horizontal axis and a vertical axis, at least a first source/drain of the plurality of the source/drains includes a first outermost portion having a flat edge and a second outermost portion having a protruding tip, wherein the first outermost portion and the second outermost portion are outermost portions that extend in opposite directions along the horizontal axis.

11. The device of claim 10 , further comprising an isolation structure disposed between the first source/drain and a second source/drain of the plurality of the source/drains, wherein an uppermost surface of the isolation structure is more elevated vertically than an uppermost surface of the first source/drain.

12. A method, comprising:

forming a first active region and a second active region over a substrate;

epitaxially growing a first source/drain component and a second source/drain component over the first active region and the second active region, respectively;

forming a material layer over the first source/drain component and the second source/drain component;

etching an opening through the material layer, wherein the opening separates the first source/drain component from the second source/drain component; and

filling the opening with one or more dielectric materials.

13. The method of claim 12 , wherein the first source/drain component and the second source/drain component merge into each other after the epitaxially growing.

14. The method of claim 12 , wherein the filling the opening includes filling the opening with a single type of dielectric material.

15. The method of claim 12 , wherein the filling the opening includes:

depositing a dielectric liner in the opening, wherein the dielectric liner partially fills the opening; and

depositing a dielectric material over the dielectric liner, wherein the dielectric material completely fills the opening.

16. The method of claim 12 , wherein the forming the material layer includes forming a sacrificial layer as the material layer, and wherein the method further includes:

removing the sacrificial layer after the opening has been etched in the sacrificial layer;

after the sacrificial layer has been removed, forming an interlayer dielectric (ILD) over and around the first source/drain component and the second source/drain component;

after the ILD has been formed, forming a metal-containing gate structure over the substrate; and

after the forming of the metal-containing gate structure, forming a first source/drain contact over the first source/drain component and forming a second source/drain contact over the second source/drain component.

17. The method of claim 16 , wherein the forming the sacrificial layer includes forming a photoresist layer as the sacrificial layer.

18. The method of claim 12 , wherein the forming the material layer includes forming an interlayer dielectric (ILD) as the material layer, and wherein the method further includes:

after the filling of the opening, forming a metal-containing gate structure over the substrate; and

after the forming of the metal-containing gate structure, forming a first source/drain contact over the first source/drain component and forming a second source/drain contact over the second source/drain component.

19. The method of claim 12 , wherein the forming the material layer includes forming an interlayer dielectric (ILD) as the material layer, and wherein the method further includes:

before the etching of the opening, forming a metal-containing gate structure over the substrate; and

after the filling the opening with the one or more dielectric materials, forming a first source/drain contact over the first source/drain component and forming a second source/drain contact over the second source/drain component.

20. The method of claim 12 , wherein the forming the material layer includes forming an interlayer dielectric (ILD) as the material layer, and wherein the method further includes, before the etching of the opening:

forming a metal-containing gate structure over the substrate; and

forming a first source/drain contact over the first source/drain component and forming a second source/drain contact over the second source/drain component;

wherein the etching of the opening is performed after the first source/drain contact and the second source/drain contact have been formed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2020
From: LIN, TA-CHUN; YEH, KUAN-LIN; LIN, CHUN-JUN; PAN, KUO-HUA; CHIANG, MU-CHI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 053813/0584 →
Continuity (1)
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