Semiconductor device which includes fins and method of making same

1. A semiconductor device which is static random access memory (SRAM), the semiconductor device comprising:

fins including all fins in the SRAM; and

wherein:

for substantially all fins, in a situation in which any given first one of the fins (first given fin) having a first width (T1) is immediately adjacent any given second one of the fins (second given fin) having a second width (T2),

the second width of the second fin is in a range as follows:

((≈80%)* T 1)≤ T 2≤((≈120%)* T 1).

2. The semiconductor device of claim 1 , further comprising:

SRAM cell regions; and

wherein:

the first and second given fins are located in one of the SRAM cell regions;

the first given fin includes a part of at least one transistor of a first conductivity type; and

the second given fin includes a part of at least one transistor of a second conductivity type, the second conductivity type being different from the first conductivity type.

3. The semiconductor device of claim 2 , wherein:

long axes of the fins are substantially parallel to a first direction;

the SRAM cell regions are arranged in pairs such that each pair includes first and second SRAM cell regions;

the first and second SRAM cell regions of each pair are substantially mirror symmetric with respect to a corresponding mirror axis; and

each mirror axis is substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction.

4. The semiconductor device of claim 1 , further comprising:

SRAM cell regions; and

wherein:

each SRAM cell region includes corresponding portions of four of the fins such that each of the four fins is partially included therein; and

three of the four fins partially included in a first SRAM cell region are continuous with three corresponding ones of the four fins which are partially included in a second SRAM cell region.

5. The semiconductor device of claim 1 , further comprising:

SRAM cell regions; and

wherein:

each SRAM cell region includes six transistors; and

the six transistors in each SRAM cell region include corresponding portions of the fins.

6. The semiconductor device of claim 1 , further comprising:

SRAM cell regions; and

wherein:

each SRAM cell region includes:

two pull-up transistors;

two pull-down transistors; and

two pass gate transistors; and

each of the transistors in each SRAM cell region includes corresponding portions of the fins.

7. The semiconductor device of claim 1 , wherein:

the first and second given fins are located in an SRAM cell region;

the first given fin includes a part of a pull up transistor; and

the second given fin includes a part of a pull down transistor.

8. A semiconductor structure comprising:

SRAM cell regions;

each SRAM cell region including:

first, second and third well regions which are non-overlapping;

first and second active regions of a first conductivity-type correspondingly over the first and third well regions;

third and fourth active regions of a second conductivity-type correspondingly over the second well region;

first and second fins correspondingly over the first and third well regions;

third and fourth fins correspondingly over the second well region;

a first gate electrode over corresponding portions of the first, third and fourth active regions;

a second gate electrode over corresponding portions of the second, third and fourth active regions; and

third gate electrode and fourth gate electrodes over corresponding portions of the first and second active region; and

wherein:

any given first instance (first given fin) and second instance (second given fin) of the first, second, third and fourth fins have corresponding first (T1) and second (T2) widths; and

in a situation in which the first given fin is immediately adjacent the second given fin, the second width of the second fin is in a range as follows:

((≈80%)* T 1)≤ T 2≤((≈120%)* T 1).

9. The semiconductor structure of claim 8 , wherein:

first and second transistors are formed at intersections of the first fin and corresponding portions of the first and third gate electrodes;

a third transistor is formed at an intersection of the third fin and a portion of the first gate electrode;

a fourth transistor is formed at an intersection of the fourth fin and a portion of the second gate electrode; and

fifth and sixth transistors are formed at intersections of the second fin and corresponding portions of the fourth and second gate electrodes.

10. The semiconductor structure of claim 9 , further comprising:

a first storage node contact over drain regions of the first, second and third transistors; and

a second storage node contact over drain regions of the fourth, fifth and sixth transistors.

11. The semiconductor structure of claim 9 , further comprising:

first and second power contacts over source regions of the corresponding third and fourth transistors, the first and second power contacts providing a first reference voltage; and

third and fourth power contacts over source regions of the corresponding first and sixth transistors, the third and fourth power contacts providing a second reference voltage.

12. The semiconductor structure of claim 11 , wherein:

the first reference voltage is VCC; and

the second reference voltage is VSS.

13. The semiconductor structure of claim 9 , further comprising:

a bit line contact over the first fin and located on a same side of the third gate electrode as a source region of the second transistor; and

a complementary bit line contact over the fourth fin and located on a same side of the fourth gate electrode as a source region of the fifth transistor.

14. The semiconductor structure of claim 8 , wherein:

long axes of the first, second, third and fourth fins are substantially parallel to a first direction;

the SRAM cell regions are arranged in pairs such that each pair includes first and second SRAM cell regions;

the first and second SRAM cell regions of each pair are substantially mirror symmetric with respect to a corresponding mirror axis; and

each mirror axis is substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction.

15. The semiconductor structure of claim 8 , wherein:

the first, second, third and fourth fins have a first height;

the semiconductor structure further comprises:

residual fins, each of the residual fins having a second height; and

the second height is substantially smaller than the first height.

16. A semiconductor device which is static random access memory (SRAM), the semiconductor device comprising:

fins including all fins in the SRAM; and

SRAM cell regions, each SRAM region including six transistors, the six transistors in each SRAM cell region include corresponding portions of the fins; and

wherein:

for substantially all fins, in a situation in which any given first one of the fins (first given fin) having a first width (T1) is immediately adjacent any given second one of the fins (second given fin) having a second width (T2),

the second width of the second fin is in a range as follows:

((≈80%)* T 1)≤ T 2≤((≈120%)* T 1).

17. The semiconductor device of claim 16 , wherein:

the first and second given fins are located in one of the SRAM cell regions;

the first given fin includes a part of at least one transistor of a first conductivity type; and

the second given fin includes a part of at least one transistor of a second conductivity type, the second conductivity type being different from the first conductivity type.

18. The semiconductor device of claim 17 , wherein:

long axes of the fins are substantially parallel to a first direction;

the SRAM cell regions are arranged in pairs such that each pair includes first and second SRAM cell regions;

the first and second SRAM cell regions of each pair are substantially mirror symmetric with respect to a corresponding mirror axis; and

each mirror axis is substantially parallel to a second direction, the second direction being substantially perpendicular to the first direction.

19. The semiconductor device of claim 16 , wherein:

each SRAM cell region includes corresponding portions of four of the fins such that each of the four fins is partially included therein; and

three of the four fins partially included in a first SRAM cell region are continuous with three corresponding ones of the four fins which are partially included in a second SRAM cell region.

20. The semiconductor device of claim 16 , wherein: further comprising:

each SRAM cell region includes:

two pull-up transistors;

two pull-down transistors; and

two pass gate transistors; and

each of the transistors in each SRAM cell region includes corresponding portions of the fins.