IP Library › Granted Patent US 12,029,143
Granted Patent B2
US 12,029,143 · App. 16/919,071 · Granted Jul 2, 2024

Memory device and programming method thereof

Inventor: Chao-I Wu (Hsinchu County, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10N70/8613H10N70/231H10N70/8413
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Quick Facts
Patent No.
US 12,029,143
App. No.
16/919,071
Granted
Jul 2, 2024
Kind
B2
Abstract

A memory device and a programming method of the memory device are provided. The memory device includes a bottom electrode, a heater, a phase change layer and a top electrode. The heater is disposed on the bottom electrode, and includes heat conducting materials different from one another in terms of electrical resistivity. A first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion. A second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials. The phase change layer is disposed on the heater and in contact with the heat conducting materials. The top electrode is disposed on the phase change layer.

Claims (37)

1. A memory device, comprising:

a bottom electrode;

a heater, disposed on the bottom electrode and comprising heat conducting materials, wherein electrical resistivities of the heat conducting materials are different from one another, a first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion, a second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials;

a phase change layer, disposed on the heater and in contact with the heat conducting materials, wherein topmost surfaces of the heat conducting materials are all in direct contact with a bottommost surface of the phase change layer; and

a top electrode, disposed on the phase change layer,

wherein the heat conducting materials are formed of the same metal nitride, a metal content in the first one of the heat conducting material is greater than a metal content in the second one of the heat conducting materials, and a nitrogen content in the first one of the heat conducting materials is less than a nitrogen content in the second one of the heat conducting materials.

2. The memory device according to claim 1 , wherein the first one of the heat conducting materials is formed as a cup shape structure with a recess inside the cup shape structure, and the second one of the heat conducting materials is disposed in a recess defined by the first one of the heat conducting materials.

3. The memory device according to claim 1 , wherein the topmost surfaces of the heat conducting materials collectively define at least a portion of a top surface of the heater.

4. The memory device according to claim 1 , wherein a third one of the heat conductive materials is accommodated in a recess defined by the second one of the heat conducting materials, and top views of the heat conducting materials are circular and concentric.

5. The memory device according to claim 4 , wherein a diameter of the first one of the heat conducting materials ranges from 10 nm to 40 nm, a diameter of the second one of the heat conducting materials ranges from 5 nm to 10 nm, and a diameter of the third one of the heat conducting materials ranges from 1 nm to 5 nm.

6. The memory device according to claim 1 , wherein the heater further comprises a heat isolation layer covering an outermost sidewall and a bottommost surface of the heat conducting materials.

7. The memory device according to claim 6 , wherein the heat isolation layer is less thermally conductive than the heat conducting materials.

8. The memory device according to claim 6 , wherein a topmost surface of the heat isolation layer and the topmost surfaces of the heat conducting materials collectively define a top surface of the heater.

9. The memory device according to claim 1 , wherein a third one of the heat conducting materials is located in a recess defined by the second one of the heat conducting materials, and is formed in a pillar shape.

10. The memory device according to claim 9 , wherein a first electrical resistivity of the first one of the heat conducting material is less than a second resistivity of the second one of the heat conducting materials, and the second resistivity is less than a third resistivity of the third one of the heat conducting materials.

11. The memory device according to claim 1 , wherein a height of the heater ranges from 30 nm to 90 nm.

12. The memory device according to claim 1 , wherein the heater has a footprint area smaller than a footprint area of the phase change layer, and smaller than a footprint area of the bottom electrode.

13. A memory device, comprising:

a bottom electrode;

a heater, disposed on the bottom electrode and having heat conducting regions configured to simultaneously produce different amounts of joule heat, wherein metallic element percentages of the heat conducting regions are different from one another;

a phase change layer, disposed on the heater and in direct contact with topmost ends of all of the heat conducting regions by a bottommost surface; and

a top electrode, disposed on the phase change layer,

wherein an outer one of the heat conducting regions has a composition of Ti x1 N y1 , an inner one of the heat conducting regions has a composition of Ti x2 N y2 , x1 is greater than x2, and y1 is smaller than y2.

14. The memory device according to claim 13 , wherein an electrical resistivity of the heater decreases outwardly from a center of the heater.

15. The memory device according to claim 13 , wherein a titanium atomic percentage and a nitrogen atomic percentage in the outer one of the heat conducting regions respectively range from 45% to 55%, a titanium atomic percentage in the inner one of the heat conducting regions ranges from 35% to 45%, and a nitrogen atomic percentage in the inner one of the heat conducting regions ranges from 55% to 65%.

16. A memory device, comprising:

a bottom electrode;

a heater, disposed on the bottom electrode and comprising heat conducting materials, wherein electrical resistivities of the heat conducting materials are different from one another, a first one of the heat conducting materials has a periphery wall portion and a bottom plate portion surrounded by the periphery wall portion, a second one of the heat conducting materials is disposed in a recess defined by the bottom plate portion and the periphery wall portion of the first one of the heat conducting materials;

a phase change layer, disposed on the heater and in direct contact with topmost surfaces of all of the heat conducting materials by a bottommost surface, and having active regions each with crystallinity independently controlled by one of the heat conducting materials, wherein a first active region of the active regions contacts the first heat conducting material, and a second active region of the active regions contacts the second heat conducting material; and

a top electrode, disposed on the phase change layer,

wherein the heat conducting materials are formed of the same metal nitride, a metal content in the first one of the heat conducting materials is greater than a metal content in the second one of the heat conducting materials, and a nitrogen content in the first one of the heat conducting materials is less than a nitrogen content in the second one of the heat conducting materials.

17. The memory device according to claim 16 , wherein the active regions are provided with different amounts of joule heat by the heat conductive materials at the same time.

18. The memory device according to claim 16 , wherein the second active region is laterally surrounded by the first active region.

19. The memory device according to claim 16 , further comprising:

a heat isolation layer, underlining and wrapping around the first one of the heat conducting materials, and in direct contact with the phase change layer.

20. The memory device according to claim 16 , further comprising:

an access transistor, formed on the semiconductor substrate, wherein the bottom electrode is connected to a source/drain terminal of the access transistor from above the access transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2020
From: WU, CHAO-I
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 053104/0917 →
Continuity (2)
Provisional Application 62968157 · Jan 31, 2020
Related Publication 20210242401A1 · Aug 5, 2021