Processing stacked substrates
Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.
1. A method of forming a microelectronic assembly, comprising:
providing a first substrate having an exposed conductive wiring layer level with or below a bonding surface of the first substrate;
coating the conductive wiring layer with one or more protective sacrificial layers;
bonding a second substrate to the one or more protective sacrificial layers using a temporary bonding layer;
removing the second substrate;
removing the temporary bonding layer;
exposing the first substrate, the one or more protective sacrificial layers, and a residue of the temporary bonding layer to a wet etchant for a preselected duration of time, the wet etchant decomposing at least one protective sacrificial layer, wherein the wet etchant comprises a complexing agent adapted to suppress dissolution of the conductive wiring layer; and
washing said at least one protective sacrificial layer and the residue of the temporary bonding layer from the conductive wiring layer.
2. The method of claim 1 , further comprising exposing the first substrate, the one or more protective sacrificial layers, and the residue to an oxygen plasma radiation for a preselected duration to modify the moisture absorption characteristics of the one or more protective sacrificial layers, prior to exposing the first substrate, the one or more protective sacrificial layers, and the residue to the wet etchant.
3. The method of claim 1 , further comprising grinding, etching, or thinning the first substrate while the second substrate is bonded to the first substrate.
4. The method of claim 1 , wherein one or more of the protective sacrificial layers comprises an inorganic silicon dioxide (SiO2), boron doped silicon dioxide (B—SiO2), or phosphorus doped silicon dioxide (P—SiO2) material.
5. The method of claim 1 , wherein the one or more protective sacrificial layers comprises an organic protective layer over the conductive wiring layer and an inorganic protective layer over the organic protective layer, the organic protective layer adapted to protect the conductive wiring layer from degradation due to removal of the inorganic protective layer and the residue.
6. The method of claim 1 , wherein the wet etchant comprises a buffered oxide etchant (BHF) or hydrofluoric acid (HF).
7. The method of claim 1 , wherein the said at least one protective sacrificial layer and the residue of the temporary bonding layer are removed from the conductive wiring layer using a room-temperature process.
8. The method of claim 1 , wherein at least one of the one or more protective sacrificial layers is applied using spin coating, plasma physical vapor deposition (PVD), or using an electrophoretic process.
9. The method of claim 1 , wherein the first substrate is singulated before removal of at least one of the one or more protective sacrificial layers.
10. The method of claim 9 , wherein the at least one of the one or more protective sacrificial layers is adapted to protect the conductive wiring layer from residue resulting from singulating the first substrate.
11. The method of claim 1 , wherein the conductive wiring layer is not degraded, roughened, or corroded by exposure to the wet etchant.
12. A method of forming a microelectronic assembly, comprising:
providing a substrate having an exposed wiring layer;
coating the wiring layer with one or more protective sacrificial layers;
singulating the substrate;
exposing the substrate and the one or more protective sacrificial layers to a wet etchant for a preselected duration of time, the wet etchant decomposing at least one protective sacrificial layer, wherein the wet etchant comprises a complexing agent adapted to suppress dissolution of the conductive wiring layer; and
washing said at least one protective sacrificial layer and residue of the singulating from the wiring layer.
13. The method of claim 12 , further comprising bonding the wiring layer of the substrate to a bonding surface of another substrate using a direct bonding technique without adhesive.
14. The method of claim 12 , further comprising:
bonding a temporary substrate to the one or more protective sacrificial layers using a temporary bonding layer;
processing the substrate while the temporary substrate is bonded to the one or more protective sacrificial layers; and
removing the temporary substrate and the temporary bonding layer.
15. The method of claim 14 , further comprising removing a residue of the temporary bonding layer and/or the singulating by removing the one or more protective sacrificial layers.
16. The method of claim 12 , further comprising removing a residue of the singulating by removing the one or more protective sacrificial layers, without degrading, roughening, or corroding the wiring layer with the wet etchant.
17. The method of claim 12 , further comprising removing a residue of the singulating by removing the one or more protective sacrificial layers, without exposing the wiring layer to the wet etchant.
18. A method of forming a microelectronic assembly, comprising:
providing a substrate having an exposed conductive wiring layer;
coating the conductive wiring layer with one or more protective sacrificial layers;
singulating the substrate;
exposing the substrate and the one or more protective sacrificial layers to a wet etchant for a preselected duration of time, the wet etchant decomposing at least one protective sacrificial layer, wherein the wet etchant comprises a complexing agent adapted to suppress dissolution of the conductive wiring layer;
washing said at least one protective sacrificial layer and a residue of the singulating from the conductive wiring layer.
19. A method of forming a microelectronic assembly, comprising:
providing a substrate having an exposed conductive wiring layer level with or below a bonding surface of the substrate;
coating the conductive wiring layer with an organic protective sacrificial layer over the conductive wiring layer and an inorganic protective sacrificial layer over the organic protective sacrificial layer, the organic protective sacrificial layer adapted to protect the conductive wiring layer from degradation due to removal of the inorganic protective sacrificial layer;
exposing the substrate and the inorganic protective sacrificial layer to a wet etchant for a preselected duration of time, the wet etchant decomposing at least the inorganic protective sacrificial layer without degrading, roughening, or corroding the conductive wiring layer.
20. The method of claim 19 , further comprising singulating the substrate prior to removing the organic protective sacrificial layer.