Memory device and programming method thereof
A programming method for a memory device includes simultaneously starting to program a first plane and a second plane; and bypassing the first plane and keeping programming the second plane when the first plane has been programmed successfully and the second plane has not been programmed successfully yet.
1. A programming method for a memory device, the programming method comprising:
simultaneously starting to program a plurality of planes, wherein the plurality of planes comprises a first plane and a second plane; and
bypassing the first plane and keeping programming the second plane when the first plane has been programmed successfully and the second plane has not been programmed successfully yet, wherein successfully-programmed planes of the plurality of planes are bypassed and others of the plurality of planes are kept being programmed.
2. The programming method of claim 1 , further comprising:
simultaneously starting to program a plurality of first memory cells of the first plane and a plurality of second memory cells of the second plane; and
bypassing the plurality of first memory cells and keeping programming the plurality of second memory cells when less than a preset number of the plurality of first memory cells has not been programmed successfully yet and more than the preset number of the plurality of second memory cells has not been programmed successfully yet.
3. The programming method of claim 2 , wherein a first programming process for the plurality of first memory cells and a second programming process for the plurality of second memory cells are initiated simultaneously but end non-simultaneously.
4. The programming method of claim 3 , further comprising:
simultaneously starting to program a plurality of third memory cells of the first plane and a plurality of fourth memory cells of the second plane after the first programming process and the second programming process are finished, wherein the plurality of first memory cells are followed by the plurality of third memory cells, wherein the plurality of second memory cells are followed by the plurality of fourth memory cells.
5. The programming method of claim 2 , wherein the plurality of first memory cells corresponds to a first programming pulse count, wherein the plurality of second memory cells of the second block corresponds to a second programming pulse count, wherein the first programming pulse count is less than the second programming pulse counts.
6. The programming method of claim 5 , further comprising:
reporting a programming failure for the second plane when the second programming pulse count is larger than a predetermined programming pulse count.
7. The programming method of claim 2 , further comprising:
verifying whether the plurality of first memory cells and the plurality of second memory cells have been programmed successfully, wherein a first number of times for the plurality of first memory cells to be verified is less than a second number of times for the plurality of second memory cells to be verified.
8. The programming method of claim 2 , wherein the first plane is suspended when the plurality of first memory cells are bypassed.
9. The programming method of claim 1 , wherein the step of bypassing the first plane comprises:
blocking a plane selection signal;
blocking a block selection signal;
deselecting all word lines of the first plane; or
deselecting all bit lines of the first plane.
10. A memory device, comprising:
a first plane;
a second plane; and
a control circuit, configured to control the first plane and the second plane according to a programming method, wherein the programming method comprises:
simultaneously starting to program a plurality of planes, wherein the plurality of planes comprises a first plane and a second plane; and
bypassing the first plane and keeping programming the second plane when the first plane has been programmed successfully and the second plane has not been programmed successfully yet, wherein successfully-programmed planes of the plurality of planes are bypassed and others of the plurality of planes are kept being programmed.
11. The memory device of claim 10 , wherein the programming method further comprising:
simultaneously starting to program a plurality of first memory cells of the first plane and a plurality of second memory cells of the second plane; and
bypassing the plurality of first memory cells and keeping programming the plurality of second memory cells when less than a preset number of the plurality of first memory cells has not been programmed successfully yet and more than the preset number of the plurality of second memory cells has not been programmed successfully yet.
12. The memory device of claim 11 , wherein a first programming process for the plurality of first memory cells and a second programming process for the plurality of second memory cells are initiated simultaneously but end non-simultaneously.
13. The memory device of claim 12 , wherein the programming method further comprising:
simultaneously starting to program a plurality of third memory cells of the first plane and a plurality of fourth memory cells of the second plane after the first programming process and the second programming process are finished, wherein the plurality of first memory cells is followed by the plurality of third memory cells, wherein the plurality of second memory cells is followed by the plurality of fourth memory cells.
14. The memory device of claim 11 , wherein the plurality of first memory cells corresponds to a first programming pulse count, wherein the plurality of second memory cells of the second block corresponds to a second programming pulse count, wherein the first programming pulse count is less than the second programming pulse counts.
15. The memory device of claim 14 , wherein the programming method further comprising:
reporting a programming failure for the second plane when the second programming pulse count is larger than a predetermined programming pulse count.
16. The memory device of claim 11 , wherein the programming method further comprising:
verifying whether the plurality of first memory cells and the plurality of second memory cells have been programmed successfully, wherein a first number of times for the plurality of first memory cells to be verified is less than a second number of times for the plurality of second memory cells to be verified.
17. The memory device of claim 11 , wherein the first plane is suspended when the plurality of first memory cells are bypassed.
18. The memory device of claim 10 , wherein the step of bypassing the first plane comprises:
blocking a plane selection signal;
blocking a block selection signal;
deselecting all word lines of the first plane; or
deselecting all bit lines of the first plane.