IP Library Granted Patent US 11,631,620
Granted Patent B2
US 11,631,620 · App. 16/923,540 · Granted Apr 18, 2023

Semiconductor device and method of testing a semiconductor device

Inventors: Hiroaki Takasu (Tokyo, JP); Yoko Serizawa (Tokyo, JP); Hiroya Suzuki (Tokyo, JP); Sumitaka Goto (Tokyo, JP)
Assignee: ABLIC INC.
H01L22/34G01R31/2884H01L22/14
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Quick Facts
Patent No.
US 11,631,620
App. No.
16/923,540
Granted
Apr 18, 2023
Kind
B2
Abstract

Provided is a semiconductor device that allows reduction of a measurement time of a PCMTEG and improvement of productivity in an IC manufacturing process. A PCMTEG region 100 formed on a surface of a semiconductor substrate is divided into a main PCMTEG region 101 and a sub-PCMTEG region 102 , and TEGs having specifications for their electrical characteristic values are all collectively arranged in the sub-PCMTEG region 102.

Claims (14)

1. A semiconductor device, comprising:

a semiconductor substrate;

a process control monitor test element group (PCMTEG) region formed on a surface of the semiconductor substrate, the PCMTEG has a plurality of test-element-groups (TEGs) each of which is classified by a type;

a main PCMTEG region and a sub-PCMTEG region arranged in the PCMTEG region; and

wherein: some of the TEGs having specifications for electrical characteristic values selected from respective types of the TEGs are arranged in the sub-PCMTEG region, and

the TEGs having no specifications for electrical characteristic values are arranged in the main PCMTEG region.

2. The semiconductor device according to claim 1 , wherein some of the TEGs having specifications for electrical characteristic values are further arranged in the main PCMTEG region.

3. The semiconductor device according to claim 1 , wherein the types of the TEGs include at least an N-type MOS transistor, a P-type MOS transistor, a resistor, and a capacitor.

4. The semiconductor device according to claim 1 , further comprising a TEG for checking probing is arranged adjacent to the sub-PCMTEG region.

5. A method of testing a semiconductor device having a process control monitor test element group (PCMTEG) region formed on a surface of a semiconductor substrate, the method comprising:

identifying a sub-PCMTEG region in the PCMTEG region, test-element-groups (TEGs) being arranged in the sub-PCMTEG region;

checking probing through use of a TEG for checking probing;

performing probing test with respect to all TEGs in the sub-PCMTEG region in order from a TEG arranged closer to the TEG for checking probing; and

determining electrical characteristic values of the all TEGs in the sub-PCMTEG region with reference to specifications.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2020
From: TAKASU, HIROAKI; SERIZAWA, YOKO; SUZUKI, HIROYA; GOTO, SUMITAKA
To: ABLIC INC.
Reel/Frame 053164/0251 →