Integrated access control system
Disclosed embodiments provide an integrated access control system. The integrated access control system includes both credential reader functionality and door controller functionality in the same package. In embodiments, the circuitry is miniaturized to fit within a standard “single gang” box such as those used for a standard light switch or receptacle. In this way, the integrated access control system of disclosed embodiments installs easily and unobtrusively in standard sized openings. To operate in a confined area such as a single gang box enclosure, a variety of thermal management and power management techniques are employed to provide reliable operation.
1. An integrated access system, comprising:
a processor;
a memory coupled to the processor;
one or more credential transceivers;
a power monitoring circuit;
one or more light emitting diodes;
a communication interface;
a proximal motion detection circuit;
a lock interface configured and disposed to operate an electronically activated lock; wherein the memory contains instructions, that when executed by the processor, perform the steps of:
detecting a low power condition from the power monitoring circuit;
sending a low power condition message to a remote computing device; and
setting a lock force reduction mode in response to the low power condition; and
reverting the lock force reduction mode for a predetermined time interval, in response to detection of motion from the proximal motion detection circuit; and wherein the memory further contains instructions for setting the lock force reduction mode that cause the processor to perform pulse width modulation of a power signal supplied to the electronically activated lock, wherein the total cycle of the power signal has a value ranging from 400 milliseconds to 700 milliseconds.
2. The integrated access system of claim 1 , wherein the memory contains instructions, that when executed by the processor, perform the pulse width modulation with a duty cycle of 0.5.
3. The integrated access system of claim 1 , wherein the proximal motion detection circuit includes a passive infrared sensor.
4. The integrated access system of claim 1 , wherein the memory contains instructions, that when executed by the processor, restores the lock force reduction mode in response to the proximal motion detection circuit detecting a predetermined period of lack of proximity motion.
5. The integrated access system of claim 4 , wherein the predetermined period of lack of proximity motion is five seconds.
6. The integrated access system of claim 1 , wherein the memory contains instructions, that when executed by the processor, cause the processor to send and receive encrypted messages to the one or more credential transceivers.
7. An integrated access system, comprising:
a processor;
a memory coupled to the processor;
one or more credential transceivers;
a power monitoring circuit;
one or more light emitting diodes;
a backup battery;
a proximal motion detection circuit;
a communication interface;
a lock interface configured and disposed to operate an electronically activated lock; wherein the memory contains instructions, that when executed by the processor, perform the steps of:
detecting a loss of AC power from the power monitoring circuit;
receiving power from the backup battery in response to detecting the loss of AC power;
monitoring backup battery voltage at a predetermined time interval; and
setting a lock force reduction mode in response to detecting a decrease in backup battery voltage below a predetermined voltage level, wherein the lock force reduction mode comprises a reduction in power supplied to the electronically activated lock while still maintaining the electronically activated lock in a locked state; and
temporarily transitioning from the lock force reduction mode to a normal lock force while operating on battery power in response to detecting motion from the proximal motion detection circuit and wherein the memory further contains instructions for setting the lock force reduction mode that cause the processor to perform pulse width modulation of a power signal supplied to the electronically activated lock, wherein the total cycle of the power signal has a value ranging from 400 milliseconds to 700 milliseconds.
8. The integrated access system of claim 7 , wherein the memory further contains instructions, that when executed by the processor, cause the processor to set a reduced transceiver activity mode.
9. The integrated access system of claim 8 , wherein the reduced transceiver activity mode includes a transceiver duty cycle ranging from 0.2 to 0.3.
10. The integrated access system of claim 8 , wherein the memory further contains instructions, that when executed by the processor, cause the processor to perform the step of reverting the reduced transceiver activity mode for a predetermined duration in response to detecting a proximal access card from the one or more credential transceivers.
11. The integrated access system of claim 7 , wherein the memory contains instructions, that when executed by the processor, perform the pulse width modulation with a duty cycle of 0.5.
12. The integrated access system of claim 7 , further comprising a proximal motion detection circuit; and wherein the memory contains instructions, that when executed by the processor, perform the step of reverting the lock force reduction mode in response to detection of motion from the proximal motion detection circuit.
13. An integrated access system, comprising:
a processor;
a memory coupled to the processor;
one or more credential transceivers;
one or more light emitting diodes;
a communication interface;
a proximal motion detection circuit;
a lock interface configured and disposed to operate an electronically activated lock; wherein the memory contains instructions, that when executed by the processor, perform the steps of:
establishing communication with the one or more credential transceivers via a cryptographically secured protocol;
in response to detecting a low power condition:
sending a low power condition message to a remote computing device; and
setting a lock force reduction mode in response to the low power condition; and
reverting the lock force reduction mode for a predetermined time interval, in response to detection of motion from the proximal motion detection circuit and wherein the memory further contains instructions for setting the lock force reduction mode that cause the processor to perform pulse width modulation of a power signal supplied to the electronically activated lock, wherein the total cycle of the power signal has a value ranging from 400 milliseconds to 700 milliseconds.
14. The integrated access system of claim 13 , wherein the cryptographically secured protocol includes the Open Supervised Device Protocol.
15. The integrated access system of claim 13 , wherein the cryptographically secured protocol includes AES-128 encryption.
16. The integrated access system of claim 13 , wherein the cryptographically secured protocol includes Cipher-based Message Authentication Code (CMAC) chaining.
17. The integrated access system of claim 7 , wherein the predetermined time interval comprises 300 seconds.