Semiconductor device structure with uniform threshold voltage distribution and method of forming the same

1. A method, comprising:

forming a fin structure extending above a dielectric isolation structure disposed over a substrate;

forming a semiconductor liner layer on exposed surfaces of the fin structure;

forming a first capping layer over the dielectric isolation structure, the first capping layer laterally surrounding a bottom portion of the semiconductor liner layer, the bottom portion of the semiconductor liner layer laterally surrounding a bottom portion of the fin structure;

forming a second capping layer over an upper portion of the semiconductor liner layer, the upper portion of the semiconductor liner layer laterally surrounding an upper portion of the fin structure; and

annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon to drive a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in the bottom portion of the fin structure is different from a dopant concentration profile in the upper portion of the fin structure.

2. The method of claim 1 , wherein the second capping layer is a material different from the first capping layer.

3. The method of claim 1 , wherein the first capping layer is a nitride-containing layer, and wherein the second capping layer is an oxide-containing layer.

4. The method of claim 3 , wherein, after the annealing, a center region of the upper portion of the fin structure is free from the dopant from the semiconductor liner layer, and wherein the dopant concentration profile in the bottom portion of the fin structure is substantially uniform.

5. The method of claim 1 , wherein the dopant includes germanium, and wherein the fin structure includes silicon.

6. The method of claim 5 , wherein, after the annealing, the dopant concentration profile in the upper portion of the fin structure is substantially uniform, and wherein a center region of the lower portion of the fin structure is free from the dopant from the semiconductor liner layer.

7. The method of claim 1 , wherein the annealing is performed at a temperature in a range from about 900 degrees Celsius to about 1100 degrees Celsius.

8. The method of claim 1 , wherein the annealing is performed for a duration in a range from about 5 seconds to about 60 seconds.

9. The method of claim 1 , further comprising:

after the annealing, removing the first capping layer and the second capping layer to expose the semiconductor liner layer and a top surface of the dielectric isolation structure;

trimming the fin structure to remove the semiconductor liner layer, the trimming resulting in a trimmed fin structure with substantially vertical sidewalls; and

forming a gate stack over the trimmed fin structure.

10. A method, comprising:

forming a fin structure including a source region, a drain region, and a channel region interposed between the source region and the drain region;

processing the channel region of the fin structure such that a threshold voltage is uniform across a height of the fin structure, the processing including:

forming a semiconductor liner layer including a dopant over the channel region of the fin structure;

forming a first capping layer to physically contact a bottom portion of the semiconductor liner layer;

forming a second capping layer to physically contact an upper portion of the semiconductor liner layer; and

annealing the channel region of the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon, the annealing causing the dopant of the semiconductor liner layer to diffuse into the channel region of the fin structure, wherein an average dopant concentration in a bottom portion of the channel region is different from an average dopant concentration in an upper portion of the channel region;

etching the channel region of the fin structure to remove the first capping layer, the second capping layer, and the semiconductor liner layer, the etching forming a trimmed fin structure; and

forming a gate structure over the channel region of the trimmed fin structure.

11. The method of claim 10 , wherein the dopant includes germanium, and wherein the fin structure includes silicon.

12. The method of claim 10 , wherein the fin structure is a fin structure of a p-type transistor device.

13. The method of claim 10 , wherein a difference between the average dopant concentration in the bottom portion of the channel region and the average dopant concentration in the upper portion of the channel region is in a range from about 3% to about 10%.

14. The method of claim 10 , wherein the first capping layer is a nitride-containing layer, and wherein the second capping layer is an oxide-containing layer.

15. The method of claim 14 , wherein, after the annealing, a core region of the upper portion of the channel region is free from the dopant, and wherein the average dopant concentration in the bottom portion of the channel region is substantially uniform.

16. The method of claim 10 , wherein

the annealing is performed at a temperature in a range from about 900 degrees Celsius to about 1100 degrees Celsius, and

the annealing is performed for a duration in a range from about 5 seconds to about 60 seconds.

17. The method of claim 10 , wherein, after the annealing, the average dopant concentration in the upper portion of the channel region is substantially uniform, and wherein a core region of the lower portion of the channel region is free from the dopant.

18. A method, comprising:

forming a fin structure of a first semiconductor material and extending above a dielectric isolation structure disposed over a substrate;

forming a semiconductor liner layer of a second semiconductor material on exposed surfaces of the fin structure, the second semiconductor material is different from the first semiconductor material in composition;

forming a first capping layer over the dielectric isolation structure, the first capping layer laterally surrounding a bottom portion of the semiconductor liner layer, the bottom portion of the semiconductor liner layer laterally surrounding a bottom portion of the fin structure;

forming a second capping layer over an upper portion of the semiconductor liner layer, the upper portion of the semiconductor liner layer laterally surrounding an upper portion of the fin structure and the second capping layer contacting the first capping layer;

annealing the fin structure having the semiconductor liner layer, the first capping layer, and the second capping layer thereon to drive a dopant from the semiconductor liner layer into the fin structure, wherein a dopant concentration profile in the bottom portion of the fin structure is different from a dopant concentration profile in the upper portion of the fin structure;

performing an etching process to remove the first capping layer and the second capping layer; and

trimming the fin structure to remove non-activated portions of the semiconductor liner layer, the trimming resulting in a trimmed fin structure with substantially vertical sidewalls.

19. The method of claim 18 , wherein the first capping layer is a nitride-containing layer, and wherein the second capping layer is an oxide-containing layer.

20. The method of claim 18 , wherein, after the annealing,

a center region of the upper portion of the fin structure is free from the dopant from the semiconductor liner layer; and

the dopant concentration profile in the bottom portion of the fin structure is substantially uniform.