Semiconductor device including two-dimensional semiconductor material
Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.
1. A semiconductor device comprising:
a substrate;
a gate electrode on the substrate, the gate electrode having a shape with a height greater than a width;
a gate dielectric on the gate electrode;
a channel layer on the gate dielectric, the channel layer comprising a two-dimensional semiconductor material; and
a source electrode and a drain electrode electrically connected to the channel layer,
wherein the channel layer has a thickness of greater than 0 nm and about 10 nm or less,
wherein the gate dielectric has a multilayer structure, and includes a ferroelectric material and a charge trapping material,
wherein the height of the gate electrode is defined at a location of the gate electrode not vertically overlapping the source electrode and the drain electrode, and
wherein, at the location of the gate electrode not vertically overlapping the source electrode and the drain electrode, the height of the gate electrode is defined from a lowermost surface of the gate electrode to an uppermost surface of the gate electrode.
2. The semiconductor device of claim 1 , wherein the substrate comprises an insulating material.
3. The semiconductor device of claim 2 , wherein the substrate further comprises a semiconductor material.
4. The semiconductor device of claim 1 , wherein the gate electrode has a height/width ratio that is greater than about 1 but less than about 20.
5. The semiconductor device of claim 1 , wherein the gate electrode comprises a metallic material or a conductive oxide.
6. The semiconductor device of claim 1 , wherein the gate electrode comprises a conductive layer and a dielectric, and the dielectric is in the conductive layer.
7. The semiconductor device of claim 1 , wherein the two-dimensional semiconductor material comprises graphene, black phosphorus, a transition metal dichalcogenide (TMD), or a combination thereof.
8. The semiconductor device of claim 1 , wherein the source electrode and the drain electrode overlap the gate electrode.
9. The semiconductor device of claim 1 , wherein
the gate dielectric includes a first dielectric and a second dielectric,
the first dielectric extends from a first end portion of the gate electrode,
the second dielectric extends from a second end portion of the gate electrode, and
the source electrode and the drain electrode overlap the first dielectric and the second dielectric, respectively.
10. The semiconductor device of claim 1 , further comprising:
an interconnect in the substrate, the interconnect being electrically connected to the gate electrode.
11. The semiconductor device of claim 1 , further comprising:
an interconnect on an upper portion of the gate electrode, the interconnect being electrically connected to the gate electrode.
12. A semiconductor device comprising:
a substrate;
a gate electrode on an upper surface of the substrate;
a gate dielectric on the substrate, the gate dielectric including a portion covering the gate electrode and having a shape with a height greater than a width;
a channel layer on the gate electric and the gate electrode, the channel layer comprising a two-dimensional semiconductor material; and
a source electrode and a drain electrode electrically connected to the channel layer,
wherein the channel layer has a thickness of greater than 0 nm and about 10 nm or less,
wherein the gate dielectric has a multilayer structure, and includes a ferroelectric material and a charge trapping material,
wherein the height of the gate electrode is defined at a location of the gate electrode not vertically overlapping the source electrode and the drain electrode, and
at the location of the gate electrode not vertically overlapping the source electrode and the drain electrode, the height of the gate electrode is defined from a lowermost surface of the gate electrode to an uppermost surface of the gate electrode.
13. The semiconductor device of claim 12 , wherein the substrate comprises an insulating material.
14. The semiconductor device of claim 12 , wherein the two-dimensional semiconductor material comprises graphene, black phosphorus, a transition metal dichalcogenide (TMD), or a combination thereof.
15. The semiconductor device of claim 12 , wherein a ratio of the height of the gate electrode to a width of the gate electrode is greater than about 1 and less than about 20.