Phase lock loops (PLLS) and methods of initializing PLLS

1. A phase lock loop (PLL) comprising:

a phase detector configured to output a signal indicative of a phase difference between a reference signal and a feedback signal;

a loop filter configured to filter an output of the phase detector;

a voltage-controlled oscillator (VCO) configured to output an oscillating signal having a frequency corresponding to an output of the loop filter;

a frequency divider configured to output the feedback signal by frequency dividing the oscillating signal output by the VCO; and

a reset circuit configured to reset the frequency divider in an initialization mode such that a phase difference between the reference signal and the feedback signal corresponds to a lock angle of the PLL.

2. The PLL of claim 1 , wherein the reset circuit is a delay circuit configured to delay the reference signal by the lock angle of the PLL and to apply the delayed reference signal as a reset signal to the frequency divider.

3. The PLL of claim 2 , wherein the delay circuit is programmable.

4. The PLL of claim 1 , wherein the reset circuit is a counter activated in response to the reference signal.

5. The PLL of claim 4 , wherein a terminal count of the counter is programmable to correspond in duration to the lock angle of the PLL.

6. The PLL of claim 5 , wherein the counter is configured to reset the frequency divider when a count value reaches the terminal count.

7. The PLL of claim 4 , wherein the reference signal is a fractional-R divided clock signal, and wherein the reset circuit is activated in response to a cycle of the reference signal having a phase in a vicinity of an average phase of the reference signal.

8. The PLL of claim 1 , further comprising a frequency multiplier configured to multiply a frequency of the oscillating signal output by the VCO and to apply a resultant multiplied frequency signal as an input to the frequency divider.

9. The PLL of claim 1 , wherein the frequency divider is a fractional-N frequency divider.

10. A method of initializing a phase lock loop (PLL), the PLL including a frequency divider in a feedback loop between an output of a voltage-controlled oscillator (VCO) and an input to a phase detector, the phase detector comparing a phase between a reference signal and an output of the frequency divider to drive the VCO, the method comprising:

programming a terminal count of a programmable counter such that a count duration to the terminal count corresponds to a duration of a lock angle of the PLL at a reference frequency of the reference signal;

activating the counter upon detecting a given phase angle of the reference signal; and

presetting the frequency divider when a count value of the counter reaches the terminal count.

11. The method of claim 10 , wherein the given phase angle of the reference signal is a positive edge or negative edge of the reference signal.

12. The method of claim 10 , further comprising closing the feedback loop upon presetting the phase angle of the frequency divider.

13. The method of claim 10 , wherein the frequency divider is a fractional-N frequency divider.

14. The method of claim 13 , wherein the reference signal is a fractional-R divided clock signal, and wherein the frequency divider of the PLL is preset in response to a cycle of the reference signal having a phase in a vicinity of an average phase of the reference signal.

15. A method of initializing a phase lock loop (PLL), the PLL including a frequency divider in a feedback loop between an output of a voltage-controlled oscillator (VCO) and an input to a phase detector, the phase detector comparing a phase between a reference signal and an output of frequency divider to drive the VCO, wherein the reference signal is a fractional-R divided clock signal, the method comprising:

activating a counter upon detecting a positive edge or negative edge of the reference signal in a cycle of the reference signal having a phase in a vicinity of an average phase of the reference signal;

presetting, in response to the counter reaching a terminal count, the frequency divider of the PLL such that a difference between the phase angle of the reference signal and a phase angle of the frequency divider output corresponds to a lock angle of the PLL.

16. The method of claim 15 , further comprising closing the feedback loop upon presetting the phase angle of the frequency divider.