IP Library › Granted Patent US 11,665,978
Granted Patent B2
US 11,665,978 · App. 16/930,291 · Granted May 30, 2023

Semiconductor device and method for fabricating the same

Inventors: Jia-Rong Wu (Kaohsiung, TW); Rai-Min Huang (Taipei, TW); I-Fan Chang (Tainan, TW); Ya-Huei Tsai (Tainan, TW); Yu-Ping Wang (Hsinchu, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H10N50/80H10B61/22H10N50/01
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Quick Facts
Patent No.
US 11,665,978
App. No.
16/930,291
Granted
May 30, 2023
Kind
B2
Abstract

A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first patterned mask on the first IMD layer, in which the first patterned mask includes a first slot extending along a first direction; forming a second patterned mask on the first patterned mask, in which the second patterned mask includes a second slot extending along a second direction and the first slot intersects the second slot to form a third slot; and forming a first metal interconnection in the third slot.

Claims (17)

1. A method for fabricating a semiconductor device, comprising:

forming a first inter-metal dielectric (IMD) layer on a substrate;

forming a first metal interconnection in the first IMD layer;

forming a second IMD layer on the first IMD layer and the first metal interconnection;

forming a first patterned mask on the second IMD layer, wherein the first patterned mask comprises a first slot extending along a first direction and overlapping the first metal interconnection;

forming a second patterned mask on the first patterned mask, wherein the second patterned mask comprises a second slot extending along a second direction and the first slot intersects the second slot to form a third slot;

removing the second IMD layer through the third slot to form a contact hole; and

forming a conductive layer in the contact hole to form a second metal interconnection for electrically connecting the first metal interconnection;

forming a magnetic tunneling junction (MTJ) stack on the second IMD layer and the second metal interconnection; and

patterning the MTJ stack to form a MTJ on the second metal interconnection, wherein an area of the MTJ is smaller than an area of the second metal interconnection.

2. The method of claim 1 , wherein the first patterned mask and the second patterned mask comprise different materials.

3. The method of claim 1 , wherein the first patterned mask comprises a metal mask.

4. The method of claim 1 , wherein the second patterned mask comprises a patterned resist.

5. The method of claim 1 , wherein the first slot comprises a rectangular slot.

6. The method of claim 1 , wherein the second slot comprises a rectangular slot.

7. The method of claim 1 , wherein the third slot comprises a square slot.

8. The method of claim 1 , wherein the first direction is orthogonal to the second direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2020
From: WU, JIA-RONG; HUANG, RAI-MIN; CHANG, I-FAN; TSAI, YA-HUEI; WANG, YU-PING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 053222/0510 →
Priority Claims (1)
CN 202010546969.4 · Jun 16, 2020 · national
Continuity (1)
Related Publication 20210391531A1 · Dec 16, 2021