Method of forming a gate structure
Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.
1. A method, comprising:
forming, over a channel region of an active region, a dummy gate stack comprising a first semiconductor material;
forming a source/drain feature over a source/drain region of the active region, the source/drain region being adjacent the channel region;
after the forming of the source/drain feature, depositing a first dielectric layer over the dummy gate stack and the source/drain feature using a first process;
after the depositing of the first dielectric layer, implanting the workpiece with a second semiconductor material different from the first semiconductor material;
after the implanting, annealing the dummy gate stack; and
replacing the dummy gate stack with a metal gate stack.
2. The method of claim 1 ,
wherein the first semiconductor material comprises silicon,
wherein the second semiconductor material comprises germanium.
3. The method of claim 1 , further comprising:
before the implanting, depositing a second dielectric layer over the first dielectric layer using a second process different from the first process; and
planarizing the workpiece to expose the dummy gate stack.
4. The method of claim 3 , wherein the first process is a flowable chemical vapor deposition (FCVD) process and the second process is a plasma-enhanced chemical vapor deposition (PECVD) process.
5. The method of claim 3 , further comprising:
depositing a gate spacer layer over the dummy gate stack,
wherein the implanting of the workpiece implants the gate spacer layer and the first dielectric layer with the second semiconductor material.
6. The method of claim 1 , wherein the annealing comprises microsecond annealing.
7. The method of claim 1 , wherein the annealing comprises a temperature between about 500° C. and about 650° C.
8. A method, comprising:
forming, over a workpiece, a dummy gate stack comprising silicon;
forming a source/drain feature adjacent the dummy gate stack;
after the forming of the source/drain feature, depositing a first dielectric layer over the dummy gate stack and the source/drain feature using a first process;
after the forming of the depositing of the first dielectric layer, implanting the workpiece with germanium;
after the implanting, annealing the dummy gate stack;
removing the dummy gate stack to form a gate trench; and
forming a metal gate stack in the gate trench.
9. The method of claim 8 ,
wherein the source/drain feature comprises non-carbon dopants,
wherein the source/drain feature is further doped with carbon to prevent thermal diffusion of the non-carbon dopants.
10. The method of claim 8 ,
wherein the dummy gate stack comprises a lower portion and an upper portion over the lower portion,
wherein a width of the lower portion is greater than a width of the upper portion by a first difference,
wherein the gate trench comprises a bottom portion and a top portion over the bottom portion,
wherein a width of the bottom portion is greater than a width of the top portion by a second difference,
wherein the first difference is greater than the second difference.
11. The method of claim 10 ,
wherein the implanting causes a first germanium concentration in the upper portion and a second germanium concentration in the lower portion,
wherein the first germanium concentration is greater than the second germanium concentration.
12. The method of claim 11 ,
wherein the implanting causes a tensile stress on the upper portion.
13. The method claim 11 ,
wherein the annealing causes a tensile stress on the upper portion and a compressive stress on the lower portion.
14. The method of claim 8 , wherein the annealing comprises microsecond annealing.
15. The method of claim 14 , wherein the annealing comprises a temperature between about 500° C. and about 650° C.
16. A semiconductor device, comprising:
an active region;
a gate structure disposed over the active region;
an etch stop layer disposed over sidewalls of the gate structure; and
a dielectric layer disposed over the etch stop layer,
wherein the dielectric layer comprises germanium,
wherein the etch stop layer comprises germanium.
17. The semiconductor device of claim 16 , further comprising a gate spacer layer disposed between the etch stop layer and the gate structure, wherein the gate spacer layer comprises germanium.
18. The semiconductor device of claim 16 ,
wherein the dielectric layer interfaces the etch stop layer at an interface,
wherein germanium is present at the interface.
19. The semiconductor device of claim 16 ,
wherein the dielectric layer comprises a top portion and a bottom portion,
wherein a germanium concentration in the top portion is greater than a germanium concentration in the bottom portion.
20. The semiconductor device of claim 16 , further comprising:
a source/drain feature adjacent the gate structure,
wherein the source/drain feature comprises carbon.