Forming isolation regions for separating fins and gate stacks

1. A method comprising:

forming a semiconductor fin protruding higher than top surfaces of isolation regions, wherein the isolation regions extend into a semiconductor substrate;

etching a portion of the semiconductor fin to form a trench, wherein the trench extends lower than bottom surfaces of the isolation regions, and extends into the semiconductor substrate;

filling the trench with a first dielectric material to form a first fin isolation region;

recessing the first fin isolation region to form a first recess; and

filling the first recess with a second dielectric material, wherein the first dielectric material and the second dielectric material in combination form a second fin isolation region.

2. The method of claim 1 , wherein the first dielectric material comprises a first seam, and the second dielectric material comprises a second seam overlapping the first seam.

3. The method of claim 2 further comprising removing a top portion of the second dielectric material comprising the second seam, wherein a bottom portion of the second dielectric material free from the second seam remains.

4. The method of claim 1 , wherein the first dielectric material is same as the second dielectric material.

5. The method of claim 1 further comprising:

forming a gate stack on the semiconductor fin; and

forming a gate isolation region separating the gate stack into a first portion and a second portion, wherein when the first fin isolation region is recessed, the gate isolation region is also recessed to form a second recess, and the second dielectric material is filled into the second recess.

6. The method of claim 1 further comprising:

forming a replacement gate stack on the semiconductor fin;

recessing the replacement gate stack; and

forming a dielectric hard mask over and contacting the replacement gate stack, wherein when the first fin isolation region is recessed, the dielectric hard mask is also recessed to form an additional recess, and the second dielectric material is filled into the additional recess.

7. The method of claim 1 , wherein after the recessing the first fin isolation region, a top surface of a remaining portion of the first fin isolation region is lower than an additional top surface of the semiconductor fin.

8. A method comprising:

forming isolation regions extending into a semiconductor substrate; and

forming a dielectric region comprising:

a lower portion having a first seam therein; and

an upper portion having a second seam therein, wherein the first seam is spaced apart from the second seam by a bottom part of the upper portion of the dielectric region, and wherein the lower portion comprises a first portion overlapping a portion of the isolation regions.

9. The method of claim 8 further comprising:

forming a semiconductor fin protruding higher than the isolation regions;

etching the semiconductor fin to form a first recess; and

filling a first dielectric material into the first recess, wherein a portion of the first dielectric material forms a second portion of the lower portion of the dielectric region.

10. The method of claim 9 , wherein the second portion of the lower portion of the dielectric region extends to a level lower than a bottom surface of the isolation regions.

11. The method of claim 9 further comprising:

recessing the first dielectric material to form a second recess; and

filling the second recess with a second dielectric material to form the upper portion of the dielectric region.

12. The method of claim 8 , wherein the lower portion and the upper portion have a distinguishable interface in between.

13. The method of claim 8 , wherein the lower portion and the upper portion are formed of a same material, and the lower portion and the upper portion form a distinguishable interface in between.

14. The method of claim 8 , wherein the upper portion and the lower portion are formed through conformal deposition processes.

15. The method of claim 8 further comprising depositing a dielectric liner, wherein the dielectric liner continuously extends to contact sidewalls of both the upper portion and the lower portion.

16. The method of claim 8 further comprising forming a first protruding semiconductor fin and a second protruding semiconductor fin having lengthwise directions aligned to a same straight line, wherein the dielectric region is formed between and separating the first protruding semiconductor fin from the second protruding semiconductor fin.

17. A method comprising:

forming isolation regions extending into a substrate;

forming a semiconductor fin extending upwardly from top surfaces of the isolation regions;

forming a first epitaxy semiconductor region and a second epitaxy semiconductor region extending into the semiconductor fin;

in a first formation process, forming a first dielectric region laterally between the first epitaxy semiconductor region and the second epitaxy semiconductor region, wherein the first formation process comprises:

depositing a dielectric material;

performing a planarization process on the dielectric material; and

recessing the dielectric material to form a recess; and

in a second formation process different from the first formation process, forming a second dielectric region filling the recess and over the first dielectric region, wherein the second dielectric region comprises a U-shaped bottom contacting a top surface of the first dielectric region.

18. The method of claim 17 , wherein the first dielectric region comprises a seam, and wherein a bottom surface of the second dielectric region is exposed to the seam.

19. The method of claim 17 , wherein the recessing the dielectric material is stopped when the dielectric material still has a bottom portion remaining, and wherein the bottom portion has a seam, and after the second dielectric region is formed, a bottom surface of the second dielectric region is exposed to the seam.